[llvm] r335641 - [Hexagon] Add a "generic" cpu

[Brendon Cahoon via llvm-commits]

Author: bcahoon
Date: Tue Jun 26 11:44:05 2018
New Revision: 335641

URL: http://llvm.org/viewvc/llvm-project?rev=335641&view=rev
Log:
[Hexagon] Add a "generic" cpu

Add the generic processor for Hexagon so that it can be used
with 3rd party programs that create a back-end with the
"generic" CPU. This patch also enables the JIT for Hexagon.

Differential Revision: https://reviews.llvm.org/D48571


Added:
    llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/Hexagon.td
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
    llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp

Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=335641&r1=335640&r2=335641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Tue Jun 26 11:44:05 2018
@@ -322,6 +322,10 @@ class Proc<string Name, SchedMachineMode
            list<SubtargetFeature> Features>
  : ProcessorModel<Name, Model, Features>;
 
+def : Proc<"generic", HexagonModelV60,
+           [ArchV4, ArchV5, ArchV55, ArchV60,
+            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
+            FeaturePackets, FeatureSmallData]>;
 def : Proc<"hexagonv4",  HexagonModelV4,
            [ArchV4,
             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,

Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=335641&r1=335640&r2=335641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Tue Jun 26 11:44:05 2018
@@ -92,6 +92,7 @@ HexagonSubtarget::HexagonSubtarget(const
 HexagonSubtarget &
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
+      {"generic", Hexagon::ArchEnum::V60},
       {"hexagonv4", Hexagon::ArchEnum::V4},
       {"hexagonv5", Hexagon::ArchEnum::V5},
       {"hexagonv55", Hexagon::ArchEnum::V55},

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=335641&r1=335640&r2=335641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Tue Jun 26 11:44:05 2018
@@ -309,6 +309,7 @@ static bool isCPUValid(std::string CPU)
 {
   std::vector<std::string> table
   {
+    "generic",
     "hexagonv4",
     "hexagonv5",
     "hexagonv55",

Modified: llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp?rev=335641&r1=335640&r2=335641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp Tue Jun 26 11:44:05 2018
@@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
 }
 
 extern "C" void LLVMInitializeHexagonTargetInfo() {
-  RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
+  RegisterTarget<Triple::hexagon, /*HasJIT=*/true> X(
       getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
 }

Added: llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll?rev=335641&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/generic-cpu.ll Tue Jun 26 11:44:05 2018
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=generic < %s | FileCheck %s
+
+; CHECK-NOT: invalid CPU
+
+define i32 @test(i32 %a) {
+  ret i32 0
+}