[PATCH] D48572: [Hexagon] Add a "generic" processor

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon created this revision.
bcahoon added a reviewer: kparzysz.
Herald added subscribers: llvm-commits, hiraditya.

The generic processor is added to be used with a 3rd party program that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon.


Repository:
  rL LLVM

https://reviews.llvm.org/D48572

Files:
  llvm/lib/Target/Hexagon/Hexagon.td
  llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
  llvm/test/CodeGen/Hexagon/generic-cpu.ll


Index: llvm/test/CodeGen/Hexagon/generic-cpu.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Hexagon/generic-cpu.ll
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=generic < %s | FileCheck %s
+
+; CHECK-NOT: invalid CPU
+
+define i32 @test(i32 %a) {
+  ret i32 0
+}
Index: llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
===================================================================
--- llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
+++ llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
@@ -18,6 +18,6 @@
 }
 
 extern "C" void LLVMInitializeHexagonTargetInfo() {
-  RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
+  RegisterTarget<Triple::hexagon, /*HasJIT=*/true> X(
       getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
 }
Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -309,6 +309,7 @@
 {
   std::vector<std::string> table
   {
+    "generic",
     "hexagonv4",
     "hexagonv5",
     "hexagonv55",
Index: llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -92,6 +92,7 @@
 HexagonSubtarget &
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
+      {"generic", Hexagon::ArchEnum::V60},
       {"hexagonv4", Hexagon::ArchEnum::V4},
       {"hexagonv5", Hexagon::ArchEnum::V5},
       {"hexagonv55", Hexagon::ArchEnum::V55},
Index: llvm/lib/Target/Hexagon/Hexagon.td
===================================================================
--- llvm/lib/Target/Hexagon/Hexagon.td
+++ llvm/lib/Target/Hexagon/Hexagon.td
@@ -322,6 +322,10 @@
            list<SubtargetFeature> Features>
  : ProcessorModel<Name, Model, Features>;
 
+def : Proc<"generic", HexagonModelV60,
+           [ArchV4, ArchV5, ArchV55, ArchV60,
+            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
+            FeaturePackets, FeatureSmallData]>;
 def : Proc<"hexagonv4",  HexagonModelV4,
            [ArchV4,
             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,


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