[PATCH] D48550: [PowerPC] Fix incorrectly encoded wait instruction

[Lei Huang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL335514: [PowerPC] Fix incorrectly encoded wait instruction (authored by lei, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D48550?vs=152704&id=152750#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48550

Files:
  llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
  llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s


Index: llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
===================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
@@ -97,8 +97,8 @@
 # CHECK-BE: eieio                           # encoding: [0x7c,0x00,0x06,0xac]
 # CHECK-LE: eieio                           # encoding: [0xac,0x06,0x00,0x7c]
             eieio
-# CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x7c]
-# CHECK-LE: waitimpl                        # encoding: [0x7c,0x00,0x40,0x7c]
+# CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x3c]
+# CHECK-LE: waitimpl                        # encoding: [0x3c,0x00,0x40,0x7c]
             wait 2
 # CHECK-BE: mbar 1                          # encoding: [0x7c,0x20,0x06,0xac]
 # CHECK-LE: mbar 1                          # encoding: [0xac,0x06,0x20,0x7c]
@@ -171,14 +171,14 @@
 # CHECK-LE: ptesync                         # encoding: [0xac,0x04,0x40,0x7c]
             ptesync
 
-# CHECK-BE: wait                            # encoding: [0x7c,0x00,0x00,0x7c]
-# CHECK-LE: wait                            # encoding: [0x7c,0x00,0x00,0x7c]
+# CHECK-BE: wait                            # encoding: [0x7c,0x00,0x00,0x3c]
+# CHECK-LE: wait                            # encoding: [0x3c,0x00,0x00,0x7c]
             wait
-# CHECK-BE: waitrsv                         # encoding: [0x7c,0x20,0x00,0x7c]
-# CHECK-LE: waitrsv                         # encoding: [0x7c,0x00,0x20,0x7c]
+# CHECK-BE: waitrsv                         # encoding: [0x7c,0x20,0x00,0x3c]
+# CHECK-LE: waitrsv                         # encoding: [0x3c,0x00,0x20,0x7c]
             waitrsv
-# CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x7c]
-# CHECK-LE: waitimpl                        # encoding: [0x7c,0x00,0x40,0x7c]
+# CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x3c]
+# CHECK-LE: waitimpl                        # encoding: [0x3c,0x00,0x40,0x7c]
             waitimpl
 
 # Time base instructions
Index: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
@@ -46,7 +46,7 @@
 0x7c 0x00 0x06 0xac
 
 # CHECK: waitimpl
-0x7c 0x40 0x00 0x7c
+0x7c 0x40 0x00 0x3c
 
 # CHECK: mbar 1
 0x7c 0x20 0x06 0xac
@@ -103,13 +103,13 @@
 0x7c 0x40 0x04 0xac
 
 # CHECK: wait
-0x7c 0x00 0x00 0x7c
+0x7c 0x00 0x00 0x3c
 
 # CHECK: waitrsv
-0x7c 0x20 0x00 0x7c
+0x7c 0x20 0x00 0x3c
 
 # CHECK: waitimpl
-0x7c 0x40 0x00 0x7c
+0x7c 0x40 0x00 0x3c
 
 # CHECK: mftb 2, 123                     
 0x7c 0x5b 0x1a 0xe6
Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3807,7 +3807,7 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
                            "eieio", IIC_LdStLoad, []>;
 
-def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
+def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
                          "wait $L", IIC_LdStLoad, []>;
 
 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),


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