[PATCH] D48536: AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg.segment.ptr.mir:4
+
+# FIXME: This requires additional context for what input registers are special inputs not present in MIR.
+
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tstellar wrote:
> What information is missing?
The registers used for input arguments are computed during argument lowering and stored in SIMachineFunctionInfo, which isn't serialized in MIR currently


https://reviews.llvm.org/D48536