[llvm] r335454 - Use APInt[] bit access to avoid "32-bit shift implicitly converted to 64 bits" MSVC warning. NFCI.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 25 04:38:27 PDT 2018


Author: rksimon
Date: Mon Jun 25 04:38:27 2018
New Revision: 335454

URL: http://llvm.org/viewvc/llvm-project?rev=335454&view=rev
Log:
Use APInt[] bit access to avoid "32-bit shift implicitly converted to 64 bits" MSVC warning. NFCI.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=335454&r1=335453&r2=335454&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Mon Jun 25 04:38:27 2018
@@ -949,7 +949,7 @@ Value *InstCombiner::simplifyAMDGCNMemor
     for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) {
       const unsigned Bit = 1 << SrcIdx;
       if (!!(DMaskVal & Bit)) {
-        if (!!(DemandedElts & (1 << OrigLoadIdx)))
+        if (!!DemandedElts[OrigLoadIdx])
           NewDMaskVal |= Bit;
         OrigLoadIdx++;
       }




More information about the llvm-commits mailing list