[PATCH] D48530: [DAGCombiner] In foldSelectOfConstants, use 'sub C1+1, (zext Cond)' instead of 'add (sext Cond), C1+1'

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.
Herald added a subscriber: nemanjai.

On X86, we usually end up converting the add to the sub form anyway. On PowerPC, this seems to avoid some nots in some of the cases.

The changes are in both the select_const tests are regressions. The PowerPC regression was largely just getting lucky that the sext worked well with the AssertSExt of the input. The code is now similar to another test case that uses 'add (zext Cond), C1' where that doesn't work well with the AssertSExt.

I haven't looked into the X86 regression yet, but it looks like some sort of reassociation issue.


Repository:
  rL LLVM

https://reviews.llvm.org/D48530

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/PowerPC/bool-math.ll
  test/CodeGen/PowerPC/select_const.ll
  test/CodeGen/X86/select_const.ll


Index: test/CodeGen/X86/select_const.ll
===================================================================
--- test/CodeGen/X86/select_const.ll
+++ test/CodeGen/X86/select_const.ll
@@ -254,8 +254,9 @@
 ; CHECK-LABEL: sel_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpq $42, %rdi
-; CHECK-NEXT:    sbbq $0, %rsi
-; CHECK-NEXT:    leaq 2(%rsi), %rax
+; CHECK-NEXT:    movl $2, %eax
+; CHECK-NEXT:    sbbq $0, %rax
+; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    retq
   %cmp = icmp ult i64 %x, 42
   %sel = select i1 %cmp, i64 1, i64 2
Index: test/CodeGen/PowerPC/select_const.ll
===================================================================
--- test/CodeGen/PowerPC/select_const.ll
+++ test/CodeGen/PowerPC/select_const.ll
@@ -269,7 +269,8 @@
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
 ; ALL-LABEL: select_C_Cplus1_signext:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    addi 3, 3, 42
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    subfic 3, 3, 42
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
Index: test/CodeGen/PowerPC/bool-math.ll
===================================================================
--- test/CodeGen/PowerPC/bool-math.ll
+++ test/CodeGen/PowerPC/bool-math.ll
@@ -83,9 +83,8 @@
 define i32 @low_bit_select_constants_bigger_false_same_size_result(i32 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_false_same_size_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    subfic 3, 3, 43
+; CHECK-NEXT:    ori 3, 3, 42
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
@@ -96,9 +95,8 @@
 define i64 @low_bit_select_constants_bigger_false_wider_result(i32 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_false_wider_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    subfic 3, 3, 27
+; CHECK-NEXT:    ori 3, 3, 26
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
@@ -109,9 +107,8 @@
 define i16 @low_bit_select_constants_bigger_false_narrower_result(i32 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_false_narrower_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 3, 3, 3
-; CHECK-NEXT:    clrlwi 3, 3, 31
-; CHECK-NEXT:    subfic 3, 3, 37
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    ori 3, 3, 36
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6779,10 +6779,10 @@
         return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
       }
       if (C1->getAPIntValue() + 1 == C2->getAPIntValue()) {
-        // select Cond, C1, C1+1 --> add (sext Cond), C1+1
+        // select Cond, C1, C1+1 --> sub C1+1, (zext Cond)
         if (VT != MVT::i1)
-          Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
-        return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
+          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
+        return DAG.getNode(ISD::SUB, DL, VT, N2, Cond);
       }
     }
 


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