[llvm] r335428 - [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include a Z to match other EVEX instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 23 23:29:50 PDT 2018
Author: ctopper
Date: Sat Jun 23 23:29:50 2018
New Revision: 335428
URL: http://llvm.org/viewvc/llvm-project?rev=335428&view=rev
Log:
[X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include a Z to match other EVEX instructions.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=335428&r1=335427&r2=335428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sat Jun 23 23:29:50 2018
@@ -2803,12 +2803,12 @@ multiclass avx512_fp_fpclass_all<string
defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
VecOpNode, sched, prd, "{q}">,
EVEX_CD8<64, CD8VF> , VEX_W;
- defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
- sched.Scl, f32x_info, prd>,
- EVEX_CD8<32, CD8VT1>;
- defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
- sched.Scl, f64x_info, prd>,
- EVEX_CD8<64, CD8VT1>, VEX_W;
+ defm SSZ : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
+ sched.Scl, f32x_info, prd>,
+ EVEX_CD8<32, CD8VT1>;
+ defm SDZ : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
+ sched.Scl, f64x_info, prd>,
+ EVEX_CD8<64, CD8VT1>, VEX_W;
}
defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=335428&r1=335427&r2=335428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jun 23 23:29:50 2018
@@ -1007,8 +1007,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VEXPANDPSZrr, X86::VEXPANDPSZrm, TB_NO_REVERSE },
{ X86::VFPCLASSPDZrr, X86::VFPCLASSPDZrm, 0 },
{ X86::VFPCLASSPSZrr, X86::VFPCLASSPSZrm, 0 },
- { X86::VFPCLASSSDrr, X86::VFPCLASSSDrm, TB_NO_REVERSE },
- { X86::VFPCLASSSSrr, X86::VFPCLASSSSrm, TB_NO_REVERSE },
+ { X86::VFPCLASSSDZrr, X86::VFPCLASSSDZrm, TB_NO_REVERSE },
+ { X86::VFPCLASSSSZrr, X86::VFPCLASSSSZrm, TB_NO_REVERSE },
{ X86::VGETEXPPDZr, X86::VGETEXPPDZm, 0 },
{ X86::VGETEXPPSZr, X86::VGETEXPPSZm, 0 },
{ X86::VGETMANTPDZrri, X86::VGETMANTPDZrmi, 0 },
@@ -3147,8 +3147,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VFPCLASSPSZ128rrk, X86::VFPCLASSPSZ128rmk, 0 },
{ X86::VFPCLASSPSZ256rrk, X86::VFPCLASSPSZ256rmk, 0 },
{ X86::VFPCLASSPSZrrk, X86::VFPCLASSPSZrmk, 0 },
- { X86::VFPCLASSSDrrk, X86::VFPCLASSSDrmk, TB_NO_REVERSE },
- { X86::VFPCLASSSSrrk, X86::VFPCLASSSSrmk, TB_NO_REVERSE },
+ { X86::VFPCLASSSDZrrk, X86::VFPCLASSSDZrmk, TB_NO_REVERSE },
+ { X86::VFPCLASSSSZrrk, X86::VFPCLASSSSZrmk, TB_NO_REVERSE },
// AES foldable instructions
{ X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=335428&r1=335427&r2=335428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Jun 23 23:29:50 2018
@@ -823,8 +823,8 @@ def: InstRW<[SKXWriteResGroup32], (instr
"VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
"VFPCLASSPD(Z|Z128|Z256)rr",
"VFPCLASSPS(Z|Z128|Z256)rr",
- "VFPCLASSSDrr",
- "VFPCLASSSSrr",
+ "VFPCLASSSDZrr",
+ "VFPCLASSSSZrr",
"VPBROADCASTBrr",
"VPBROADCASTWrr",
"VPCMPB(Z|Z128|Z256)rri",
@@ -1608,7 +1608,7 @@ def SKXWriteResGroup119 : SchedWriteRes<
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
- "VFPCLASSSDrm(b?)",
+ "VFPCLASSSDZrm(b?)",
"VPBROADCASTBYrm",
"VPBROADCASTB(Z|Z256)m(b?)",
"VPBROADCASTWYrm",
@@ -1768,7 +1768,7 @@ def: InstRW<[SKXWriteResGroup136], (inst
"VCMPPSZ128rm(b?)i",
"VCMPSDZrm",
"VCMPSSZrm",
- "VFPCLASSSSrm(b?)",
+ "VFPCLASSSSZrm(b?)",
"VPCMPBZ128rmi(b?)",
"VPCMPDZ128rmi(b?)",
"VPCMPEQ(B|D|Q|W)Z128rm(b?)",
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