[llvm] r335394 - [X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in memory expressions like [EAX+ESP].

[Craig Topper via llvm-commits]

Author: ctopper
Date: Fri Jun 22 14:57:24 2018
New Revision: 335394

URL: http://llvm.org/viewvc/llvm-project?rev=335394&view=rev
Log:
[X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in memory expressions like [EAX+ESP].

By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register.

There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently.

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/X86/intel-syntax.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=335394&r1=335393&r2=335394&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jun 22 14:57:24 2018
@@ -1858,6 +1858,10 @@ std::unique_ptr<X86Operand> X86AsmParser
   unsigned IndexReg = SM.getIndexReg();
   unsigned Scale = SM.getScale();
 
+  if (Scale == 1 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
+      (IndexReg == X86::ESP || IndexReg == X86::RSP))
+    std::swap(BaseReg, IndexReg);
+
   // If this is a 16-bit addressing mode with the base and index in the wrong
   // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
   // shared with att syntax where order matters.

Modified: llvm/trunk/test/MC/X86/intel-syntax.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax.s?rev=335394&r1=335393&r2=335394&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax.s Fri Jun 22 14:57:24 2018
@@ -889,3 +889,11 @@ sysret
 // CHECK: sysretq
 sysretq
 
+// CHECK: leaq (%rsp,%rax), %rax
+lea rax, [rax+rsp]
+// CHECK: leaq (%rsp,%rax), %rax
+lea rax, [rsp+rax]
+// CHECK: leal (%esp,%eax), %eax
+lea eax, [eax+esp]
+// CHECK: leal (%esp,%eax), %eax
+lea eax, [esp+eax]