[llvm] r335249 - [ARM] Enable useAA() for the in-order Cortex-R52

[David Green via llvm-commits]

Author: dmgreen
Date: Thu Jun 21 08:48:29 2018
New Revision: 335249

URL: http://llvm.org/viewvc/llvm-project?rev=335249&view=rev
Log:
[ARM] Enable useAA() for the in-order Cortex-R52

This option allows codegen (such as DAGCombine or MI scheduling) to use alias
analysis information, which can help with the codegen on in-order cpu's,
especially machine scheduling. Here I have done things the same way as AArch64,
adding a subtarget feature to enable this for specific cores, and enabled it for
the R52 where we have a schedule to make use of it.

Differential Revision: https://reviews.llvm.org/D48074


Added:
    llvm/trunk/test/CodeGen/ARM/useaa.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=335249&r1=335248&r2=335249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jun 21 08:48:29 2018
@@ -330,6 +330,10 @@ def FeatureNoPostRASched : SubtargetFeat
     "DisablePostRAScheduler", "true",
     "Don't schedule again after register allocation">;
 
+// Enable use of alias analysis during code generation
+def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
+                                    "Use alias analysis during codegen">;
+
 //===----------------------------------------------------------------------===//
 // ARM architecture class
 //
@@ -1006,7 +1010,8 @@ def : ProcNoItin<"kryo",
 
 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
                                                          FeatureUseMISched,
-                                                         FeatureFPAO]>;
+                                                         FeatureFPAO,
+                                                         FeatureUseAA]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=335249&r1=335248&r2=335249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 21 08:48:29 2018
@@ -198,6 +198,9 @@ protected:
   /// register allocation.
   bool DisablePostRAScheduler = false;
 
+  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
+  bool UseAA = false;
+
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
@@ -723,6 +726,10 @@ public:
   /// True for some subtargets at > -O0.
   bool enablePostRAScheduler() const override;
 
+  /// Enable use of alias analysis during code generation (during MI
+  /// scheduling, DAGCombine, etc.).
+  bool useAA() const override { return UseAA; }
+
   // enableAtomicExpand- True if we need to expand our atomics.
   bool enableAtomicExpand() const override;
 

Added: llvm/trunk/test/CodeGen/ARM/useaa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/useaa.ll?rev=335249&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/useaa.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/useaa.ll Thu Jun 21 08:48:29 2018
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
+
+; Check we use AA during codegen, so can interleave these loads/stores.
+
+; CHECK-LABEL: test
+; GENERIC: ldr
+; GENERIC: str
+; GENERIC: ldr
+; GENERIC: str
+; USEAA: ldr
+; USEAA: ldr
+; USEAA: str
+; USEAA: str
+
+define void @test(i32* nocapture %a, i32* noalias nocapture %b) {
+entry:
+  %0 = load i32, i32* %a, align 4
+  %add = add nsw i32 %0, 10
+  store i32 %add, i32* %a, align 4
+  %1 = load i32, i32* %b, align 4
+  %add2 = add nsw i32 %1, 20
+  store i32 %add2, i32* %b, align 4
+  ret void
+}
+