[PATCH] D48434: Fix crash on inline asm with 64bit matching input in 32bit GPR
Thomas Preud'homme via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 21 08:01:29 PDT 2018
thopre created this revision.
thopre added reviewers: efriedma, t.p.northover.
Herald added a reviewer: javed.absar.
Herald added a subscriber: llvm-commits.
Add support for inline assembly with matching input operand that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR). Note that regular input is already handled by existing code.
Repository:
rL LLVM
https://reviews.llvm.org/D48434
Files:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
test/CodeGen/ARM/pr34170.ll
Index: test/CodeGen/ARM/pr34170.ll
===================================================================
--- test/CodeGen/ARM/pr34170.ll
+++ test/CodeGen/ARM/pr34170.ll
@@ -10,4 +10,13 @@
ret double %1
}
+; Check support for returning a double in GPR with matching double input
+define double @dbl_gpr_matching_in_op(double %d) nounwind {
+; CHECK-LABEL: dbl_gpr_matching_in_op
+; CHECK: mov r1, r0
+; CHECK: vmov d0, r0, r1
+ %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
+ ret double %1
+}
+
attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" }
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7124,10 +7124,11 @@
/// uses features that we can't model on machineinstrs, we have SDISel do the
/// allocation. This produces generally horrible, but correct, code.
///
-/// OpInfo describes the operand.
+/// OpInfo describes the operand
+/// RefOpInfo describes the matching operand if any, the operand otherwise
static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
- const SDLoc &DL,
- SDISelAsmOperandInfo &OpInfo) {
+ const SDLoc &DL, SDISelAsmOperandInfo &OpInfo,
+ SDISelAsmOperandInfo &RefOpInfo) {
LLVMContext &Context = *DAG.getContext();
MachineFunction &MF = DAG.getMachineFunction();
@@ -7137,8 +7138,8 @@
// If this is a constraint for a single physreg, or a constraint for a
// register class, find it.
std::pair<unsigned, const TargetRegisterClass *> PhysReg =
- TLI.getRegForInlineAsmConstraint(&TRI, OpInfo.ConstraintCode,
- OpInfo.ConstraintVT);
+ TLI.getRegForInlineAsmConstraint(&TRI, RefOpInfo.ConstraintCode,
+ RefOpInfo.ConstraintVT);
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other) {
@@ -7180,6 +7181,11 @@
NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
}
+ // No need to allocate a matching input constraint since the constraint it's
+ // matching to has already been allocated.
+ if (OpInfo.isMatchingInputConstraint())
+ return;
+
MVT RegVT;
EVT ValueVT = OpInfo.ConstraintVT;
@@ -7428,19 +7434,27 @@
// If this constraint is for a specific register, allocate it before
// anything else.
+ SDISelAsmOperandInfo &RefOpInfo =
+ OpInfo.isMatchingInputConstraint()
+ ? ConstraintOperands[OpInfo.getMatchedOperand()]
+ : ConstraintOperands[i];
if (OpInfo.ConstraintType == TargetLowering::C_Register)
- GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
+ GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
}
// Third pass - Loop over all of the operands, assigning virtual or physregs
// to register class operands.
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
+ SDISelAsmOperandInfo &RefOpInfo =
+ OpInfo.isMatchingInputConstraint()
+ ? ConstraintOperands[OpInfo.getMatchedOperand()]
+ : ConstraintOperands[i];
// C_Register operands have already been allocated, Other/Memory don't need
// to be.
- if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
- GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
+ if (RefOpInfo.ConstraintType == TargetLowering::C_RegisterClass)
+ GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
}
// AsmNodeOperands - The operands for the ISD::INLINEASM node.
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