[llvm] r335226 - AMDGPU: Use generic tables instead of SearchableTable
Nicolai Haehnle via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 21 06:36:33 PDT 2018
Author: nha
Date: Thu Jun 21 06:36:33 2018
New Revision: 335226
URL: http://llvm.org/viewvc/llvm-project?rev=335226&view=rev
Log:
AMDGPU: Use generic tables instead of SearchableTable
Summary:
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48014
Change-Id: Ibb43f90d955275571aff17d0c3ecfb5e5b299641
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
llvm/trunk/lib/Target/AMDGPU/AMDGPUSearchableTables.td
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp?rev=335226&r1=335225&r2=335226&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp Thu Jun 21 06:36:33 2018
@@ -28,10 +28,10 @@ using namespace llvm;
namespace llvm {
namespace AMDGPU {
-#define GET_RSRCINTRINSIC_IMPL
+#define GET_RsrcIntrinsics_IMPL
#include "AMDGPUGenSearchableTables.inc"
-#define GET_D16IMAGEDIMINTRINSIC_IMPL
+#define GET_D16ImageDimIntrinsics_IMPL
#include "AMDGPUGenSearchableTables.inc"
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h?rev=335226&r1=335225&r2=335226&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h Thu Jun 21 06:36:33 2018
@@ -61,13 +61,13 @@ struct RsrcIntrinsic {
uint8_t RsrcArg;
bool IsImage;
};
-const RsrcIntrinsic *lookupRsrcIntrinsicByIntr(unsigned Intr);
+const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
struct D16ImageDimIntrinsic {
unsigned Intr;
unsigned D16HelperIntr;
};
-const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsicByIntr(unsigned Intr);
+const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
} // end AMDGPU namespace
} // End llvm namespace
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSearchableTables.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSearchableTables.td?rev=335226&r1=335225&r2=335226&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSearchableTables.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSearchableTables.td Thu Jun 21 06:36:33 2018
@@ -13,15 +13,20 @@ include "llvm/TableGen/SearchableTable.t
// Resource intrinsics table.
//===----------------------------------------------------------------------===//
-class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> : SearchableTable {
- let SearchableFields = ["Intr"];
- let EnumNameField = ?;
-
+class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> {
Intrinsic Intr = !cast<Intrinsic>(intr);
bits<8> RsrcArg = intr.RsrcArg;
bit IsImage = intr.IsImage;
}
+def RsrcIntrinsics : GenericTable {
+ let FilterClass = "RsrcIntrinsic";
+ let Fields = ["Intr", "RsrcArg", "IsImage"];
+
+ let PrimaryKey = ["Intr"];
+ let PrimaryKeyName = "lookupRsrcIntrinsic";
+}
+
foreach intr = !listconcat(AMDGPUBufferIntrinsics,
AMDGPUImageIntrinsics,
AMDGPUImageDimIntrinsics,
@@ -31,13 +36,18 @@ foreach intr = !listconcat(AMDGPUBufferI
def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
}
-class SourceOfDivergence<Intrinsic intr> : SearchableTable {
- let SearchableFields = ["Intr"];
- let EnumNameField = ?;
-
+class SourceOfDivergence<Intrinsic intr> {
Intrinsic Intr = intr;
}
+def SourcesOfDivergence : GenericTable {
+ let FilterClass = "SourceOfDivergence";
+ let Fields = ["Intr"];
+
+ let PrimaryKey = ["Intr"];
+ let PrimaryKeyName = "lookupSourceOfDivergence";
+}
+
def : SourceOfDivergence<int_amdgcn_workitem_id_x>;
def : SourceOfDivergence<int_amdgcn_workitem_id_y>;
def : SourceOfDivergence<int_amdgcn_workitem_id_z>;
@@ -84,15 +94,20 @@ def : SourceOfDivergence<int_amdgcn_ds_s
foreach intr = AMDGPUImageDimAtomicIntrinsics in
def : SourceOfDivergence<intr>;
-class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> : SearchableTable {
- let SearchableFields = ["Intr"];
- let EnumNameField = ?;
-
+class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> {
Intrinsic Intr = intr;
code D16HelperIntr =
!cast<code>("AMDGPUIntrinsic::SI_image_d16helper_" # intr.P.OpMod # intr.P.Dim.Name);
}
+def D16ImageDimIntrinsics : GenericTable {
+ let FilterClass = "D16ImageDimIntrinsic";
+ let Fields = ["Intr", "D16HelperIntr"];
+
+ let PrimaryKey = ["Intr"];
+ let PrimaryKeyName = "lookupD16ImageDimIntrinsic";
+}
+
foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
AMDGPUImageDimGatherIntrinsics) in {
def : D16ImageDimIntrinsic<intr>;
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=335226&r1=335225&r2=335226&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Jun 21 06:36:33 2018
@@ -649,7 +649,7 @@ bool SITargetLowering::getTgtMemIntrinsi
MachineFunction &MF,
unsigned IntrID) const {
if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
- AMDGPU::lookupRsrcIntrinsicByIntr(IntrID)) {
+ AMDGPU::lookupRsrcIntrinsic(IntrID)) {
AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
(Intrinsic::ID)IntrID);
if (Attr.hasFnAttribute(Attribute::ReadNone))
@@ -5138,7 +5138,7 @@ SDValue SITargetLowering::LowerINTRINSIC
Op.getValueType().isVector() &&
Op.getValueType().getScalarSizeInBits() == 16) {
if (const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
- AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrID)) {
+ AMDGPU::lookupD16ImageDimIntrinsic(IntrID)) {
return adjustLoadValueType(D16ImageDimIntr->D16HelperIntr,
cast<MemSDNode>(Op), DAG, true);
}
@@ -5393,7 +5393,7 @@ SDValue SITargetLowering::LowerINTRINSIC
}
default: {
const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
- AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrinsicID);
+ AMDGPU::lookupD16ImageDimIntrinsic(IntrinsicID);
if (D16ImageDimIntr) {
SDValue VData = Op.getOperand(2);
EVT StoreVT = VData.getValueType();
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=335226&r1=335225&r2=335226&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Thu Jun 21 06:36:33 2018
@@ -951,15 +951,15 @@ namespace {
struct SourceOfDivergence {
unsigned Intr;
};
-const SourceOfDivergence *lookupSourceOfDivergenceByIntr(unsigned Intr);
+const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
-#define GET_SOURCEOFDIVERGENCE_IMPL
+#define GET_SourcesOfDivergence_IMPL
#include "AMDGPUGenSearchableTables.inc"
} // end anonymous namespace
bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
- return lookupSourceOfDivergenceByIntr(IntrID);
+ return lookupSourceOfDivergence(IntrID);
}
} // namespace AMDGPU
} // namespace llvm
More information about the llvm-commits
mailing list