[PATCH] D48029: [DAGCombine] Fix alignment for offset loads/stores

[Dave Green via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL335210: [DAGCombine] Fix alignment for offset loads/stores (authored by dmgreen, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D48029?vs=152042&id=152237#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48029

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/ARM/alias_align.ll


Index: llvm/trunk/test/CodeGen/ARM/alias_align.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/alias_align.ll
+++ llvm/trunk/test/CodeGen/ARM/alias_align.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv8-arm-none-eabi"
+
+; Check the loads happen after the stores (note: directly returning 0 is also valid)
+; CHECK-LABEL: somesortofhash
+; CHECK-NOT: ldr
+; CHECK: str
+
+define i64 @somesortofhash() {
+entry:
+  %helper = alloca i8, i32 64, align 8
+  %helper.0.4x32 = bitcast i8* %helper to <4 x i32>*
+  %helper.20 = getelementptr inbounds i8, i8* %helper, i32 20
+  %helper.24 = getelementptr inbounds i8, i8* %helper, i32 24
+  store <4 x i32> zeroinitializer, <4 x i32>* %helper.0.4x32, align 8
+  %helper.20.32 = bitcast i8* %helper.20 to i32*
+  %helper.24.32 = bitcast i8* %helper.24 to i32*
+  store i32 0, i32* %helper.20.32
+  store i32 0, i32* %helper.24.32, align 8
+  %helper.20.64 = bitcast i8* %helper.20 to i64*
+  %load.helper.20.64 = load i64, i64* %helper.20.64, align 4
+  ret i64 %load.helper.20.64
+}
Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12231,13 +12231,14 @@
   // Try to infer better alignment information than the load already has.
   if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
     if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
-      if (Align > LD->getMemOperand()->getBaseAlignment()) {
+      if (Align > LD->getAlignment() && LD->getSrcValueOffset() % Align == 0) {
         SDValue NewLoad = DAG.getExtLoad(
             LD->getExtensionType(), SDLoc(N), LD->getValueType(0), Chain, Ptr,
             LD->getPointerInfo(), LD->getMemoryVT(), Align,
             LD->getMemOperand()->getFlags(), LD->getAAInfo());
-        if (NewLoad.getNode() != N)
-          return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
+        // NewLoad will always be N as we are only refining the alignment
+        assert(NewLoad.getNode() == N);
+        (void)NewLoad;
       }
     }
   }
@@ -14238,13 +14239,14 @@
   // Try to infer better alignment information than the store already has.
   if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
     if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
-      if (Align > ST->getAlignment()) {
+      if (Align > ST->getAlignment() && ST->getSrcValueOffset() % Align == 0) {
         SDValue NewStore =
             DAG.getTruncStore(Chain, SDLoc(N), Value, Ptr, ST->getPointerInfo(),
                               ST->getMemoryVT(), Align,
                               ST->getMemOperand()->getFlags(), ST->getAAInfo());
-        if (NewStore.getNode() != N)
-          return CombineTo(ST, NewStore, true);
+        // NewStore will always be N as we are only refining the alignment
+        assert(NewStore.getNode() == N);
+        (void)NewStore;
       }
     }
   }


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