[llvm] r335127 - [RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}

[Alex Bradbury via llvm-commits]

Author: asb
Date: Wed Jun 20 07:03:02 2018
New Revision: 335127

URL: http://llvm.org/viewvc/llvm-project?rev=335127&view=rev
Log:
[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}

These are produced by GCC and supported by GAS, but not currently contained in 
the pseudoinstruction listing in the RISC-V ISA manual.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
    llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
    llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td?rev=335127&r1=335126&r2=335127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td Wed Jun 20 07:03:02 2018
@@ -185,6 +185,13 @@ let Predicates = [HasStdExtD] in {
 def : InstAlias<"fmv.d $rd, $rs",  (FSGNJ_D  FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
+
+// fgt.d/fge.d are recognised by the GNU assembler but the canonical
+// flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.d $rd, $rs, $rt",
+                (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
+def : InstAlias<"fge.d $rd, $rs, $rt",
+                (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 } // Predicates = [HasStdExtD]
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td?rev=335127&r1=335126&r2=335127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td Wed Jun 20 07:03:02 2018
@@ -200,6 +200,13 @@ def : InstAlias<"fmv.s $rd, $rs",  (FSGN
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 
+// fgt.s/fge.s are recognised by the GNU assembler but the canonical
+// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.s $rd, $rs, $rt",
+                (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
+def : InstAlias<"fge.s $rd, $rs, $rt",
+                (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
+
 // The following csr instructions actually alias instructions from the base ISA.
 // However, it only makes sense to support them when the F extension is enabled.
 // CSR Addresses: 0x003 == fcsr, 0x002 == frm, 0x001 == fflags

Modified: llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s?rev=335127&r1=335126&r2=335127&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s Wed Jun 20 07:03:02 2018
@@ -36,6 +36,13 @@ fabs.d f1, f2
 # CHECK-ALIAS: fneg.d ft2, ft3
 fneg.d f2, f3
 
+# CHECK-INST: flt.d tp, ft6, ft5
+# CHECK-ALIAS: flt.d tp, ft6, ft5
+fgt.d x4, f5, f6
+# CHECK-INST: fle.d t2, fs1, fs0
+# CHECK-ALIAS: fle.d t2, fs1, fs0
+fge.d x7, f8, f9
+
 ##===----------------------------------------------------------------------===##
 ## Aliases which omit the rounding mode.
 ##===----------------------------------------------------------------------===##

Modified: llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s?rev=335127&r1=335126&r2=335127&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s Wed Jun 20 07:03:02 2018
@@ -36,6 +36,13 @@ fabs.s f1, f2
 # CHECK-ALIAS: fneg.s ft2, ft3
 fneg.s f2, f3
 
+# CHECK-INST: flt.s tp, ft6, ft5
+# CHECK-ALIAS: flt.s tp, ft6, ft5
+fgt.s x4, f5, f6
+# CHECK-INST: fle.s t2, fs1, fs0
+# CHECK-ALIAS: fle.s t2, fs1, fs0
+fge.s x7, f8, f9
+
 # The following instructions actually alias instructions from the base ISA.
 # However, it only makes sense to support them when the F extension is enabled.
 # CHECK-INST: csrrs t0, 3, zero