[PATCH] D48335: [DAG] Fix and-mask folding when narrowing loads.

[Nirav Dave via Phabricator via llvm-commits]

niravd created this revision.
niravd added reviewers: samparker, RKSimon, nemanjai.
Herald added a subscriber: hiraditya.

Check that and masks are strictly smaller than implicit mask from
narrowed load.

Fixes PR37820.


Repository:
  rL LLVM

https://reviews.llvm.org/D48335

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/pr37820.ll


Index: llvm/test/CodeGen/X86/pr37820.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/pr37820.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
+
+ at a = external dso_local local_unnamed_addr global i64, align 8
+ at c = external dso_local local_unnamed_addr global i64, align 8
+ at b = external dso_local local_unnamed_addr global i64, align 8
+
+; Should generate a 16-bit load
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movzwl a+{{.*}}(%rip), %eax
+; CHECK-NEXT:    movq %rax, {{.*}}(%rip)
+; CHECK-NEXT:    retq
+entry:
+  %0 = load i64, i64* @a, align 8
+  %1 = load i64, i64* @c, align 8
+  %and = and i64 %1, -16384
+  %add = add nsw i64 %and, 4503359447364223024
+  %shr = lshr i64 %0, %add
+  %conv1 = and i64 %shr, 4294967295
+  store i64 %conv1, i64* @b, align 8
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8688,8 +8688,9 @@
         if (ShiftMask.isMask()) {
           EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(),
                                            ShiftMask.countTrailingOnes());
-          // Recompute the type.
-          if (TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT))
+          // If the mask is smaller, recompute the type.
+          if ((ExtVT.getSizeInBits() > MaskedVT.getSizeInBits()) &&
+              TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT))
             ExtVT = MaskedVT;
         }
       }


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