[PATCH] D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:348
+    // bits of the underlying ZMM register.
+    if ((HasVEX || HasEVEX) && VR256XRC.contains(RegID))
+      return true;
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What should happen if you enable avx512f and xop instructions at the same time? I know no real CPU supports it, but should a 256-bit xop instruction clear the upper bits of zmm?


https://reviews.llvm.org/D48225