[llvm] r335053 - [mips] Fix the predicates of some aliases
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 19 08:25:01 PDT 2018
Author: sdardis
Date: Tue Jun 19 08:25:01 2018
New Revision: 335053
URL: http://llvm.org/viewvc/llvm-project?rev=335053&view=rev
Log:
[mips] Fix the predicates of some aliases
Previously, some aliases were marked as not being available for microMIPS32R6,
but this was overridden at the top level.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D48321
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=335053&r1=335052&r2=335053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Tue Jun 19 08:25:01 2018
@@ -1677,6 +1677,9 @@ def : MipsInstAlias<"xor $rs, $imm",
def : MipsInstAlias<"not $rt, $rs",
(NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
ISA_MICROMIPS32R6;
+def : MipsInstAlias<"not $rt",
+ (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
+ ISA_MICROMIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=335053&r1=335052&r2=335053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue Jun 19 08:25:01 2018
@@ -1287,7 +1287,7 @@ class UncondBranchMMPseudo<string opstr>
def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
-let Predicates = [InMicroMips] in {
+let EncodingPredicates = [InMicroMips] in {
def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
@@ -1374,10 +1374,10 @@ let Predicates = [InMicroMips] in {
def : MipsInstAlias<"not $rt, $rs",
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
- ISA_MICROMIPS;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"not $rt",
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
- ISA_MICROMIPS;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"bnez $rs,$offset",
(BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
ISA_MICROMIPS;
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=335053&r1=335052&r2=335053&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue Jun 19 08:25:01 2018
@@ -390,7 +390,9 @@
and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05]
and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05]
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0]
+ # CHECK-NEXT: # <MCInst #{{.*}} NOR_MMR6
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x03,0x1a,0xd0]
+ # CHECK-NEXT: # <MCInst #{{.*}} NOR_MMR6
or $3, 5 # CHECK: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05]
or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05]
xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05]
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