[llvm] r334948 - [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 18 07:47:52 PDT 2018
Author: s.desmalen
Date: Mon Jun 18 07:47:52 2018
New Revision: 334948
URL: http://llvm.org/viewvc/llvm-project?rev=334948&view=rev
Log:
[AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.
Summary:
The variants added by this patch are:
- SQINC (signed increment)
- UQINC (unsigned increment)
- SQDEC (signed decrement)
- UQDEC (unsigned decrement)
For example:
uqincw x0, all, mul #4
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Differential Revision: https://reviews.llvm.org/D47715
Added:
llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecb.s
llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecd.s
llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdech.s
llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecw.s
llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincb.s
llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincd.s
llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqinch.s
llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincw.s
llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecb.s
llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecd.s
llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdech.s
llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecw.s
llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincb.s
llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincd.s
llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqinch.s
llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincw.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=334948&r1=334947&r2=334948&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Jun 18 07:47:52 2018
@@ -527,6 +527,26 @@ let Predicates = [HasSVE] in {
defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
+ defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
+ defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
+ defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
+ defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
+
+ defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
+ defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
+ defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
+ defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
+
+ defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
+ defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
+ defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
+ defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
+
+ defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
+ defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
+ defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
+ defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
+
defm INDEX_RR : sve_int_index_rr<"index">;
defm INDEX_IR : sve_int_index_ir<"index">;
defm INDEX_RI : sve_int_index_ri<"index">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=334948&r1=334947&r2=334948&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Jun 18 07:47:52 2018
@@ -314,6 +314,37 @@ multiclass sve_int_pred_pattern_a<bits<3
(!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
}
+class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
+ RegisterOperand st>
+: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
+ asm, "\t$Rdn, $pattern, mul $imm4",
+ "",
+ []>, Sched<[]> {
+ bits<5> Rdn;
+ bits<5> pattern;
+ bits<4> imm4;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = opc{4-3};
+ let Inst{21} = 0b1;
+ let Inst{20} = opc{2};
+ let Inst{19-16} = imm4;
+ let Inst{15-12} = 0b1111;
+ let Inst{11-10} = opc{1-0};
+ let Inst{9-5} = pattern;
+ let Inst{4-0} = Rdn;
+
+ let Constraints = "$Rdn = $_Rdn";
+}
+
+multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
+ def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
+
+ def : InstAlias<asm # "\t$Rdn, $pattern",
+ (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
+ def : InstAlias<asm # "\t$Rdn",
+ (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Permute - Cross Lane Group
Added: llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqdecb w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecb w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecb wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecb sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqdecb x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecb x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecb x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecb x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqdecb x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecb x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecb x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecb x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecb x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqdecb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecb.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecb x0
+// CHECK-INST: sqdecb x0
+// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
+
+sqdecb x0, all
+// CHECK-INST: sqdecb x0
+// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
+
+sqdecb x0, all, mul #1
+// CHECK-INST: sqdecb x0
+// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
+
+sqdecb x0, all, mul #16
+// CHECK-INST: sqdecb x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 3f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqdecb x0, pow2
+// CHECK-INST: sqdecb x0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 30 04 <unknown>
+
+sqdecb x0, vl1
+// CHECK-INST: sqdecb x0, vl1
+// CHECK-ENCODING: [0x20,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 30 04 <unknown>
+
+sqdecb x0, vl2
+// CHECK-INST: sqdecb x0, vl2
+// CHECK-ENCODING: [0x40,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f8 30 04 <unknown>
+
+sqdecb x0, vl3
+// CHECK-INST: sqdecb x0, vl3
+// CHECK-ENCODING: [0x60,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f8 30 04 <unknown>
+
+sqdecb x0, vl4
+// CHECK-INST: sqdecb x0, vl4
+// CHECK-ENCODING: [0x80,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f8 30 04 <unknown>
+
+sqdecb x0, vl5
+// CHECK-INST: sqdecb x0, vl5
+// CHECK-ENCODING: [0xa0,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f8 30 04 <unknown>
+
+sqdecb x0, vl6
+// CHECK-INST: sqdecb x0, vl6
+// CHECK-ENCODING: [0xc0,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f8 30 04 <unknown>
+
+sqdecb x0, vl7
+// CHECK-INST: sqdecb x0, vl7
+// CHECK-ENCODING: [0xe0,0xf8,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f8 30 04 <unknown>
+
+sqdecb x0, vl8
+// CHECK-INST: sqdecb x0, vl8
+// CHECK-ENCODING: [0x00,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f9 30 04 <unknown>
+
+sqdecb x0, vl16
+// CHECK-INST: sqdecb x0, vl16
+// CHECK-ENCODING: [0x20,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f9 30 04 <unknown>
+
+sqdecb x0, vl32
+// CHECK-INST: sqdecb x0, vl32
+// CHECK-ENCODING: [0x40,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f9 30 04 <unknown>
+
+sqdecb x0, vl64
+// CHECK-INST: sqdecb x0, vl64
+// CHECK-ENCODING: [0x60,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f9 30 04 <unknown>
+
+sqdecb x0, vl128
+// CHECK-INST: sqdecb x0, vl128
+// CHECK-ENCODING: [0x80,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f9 30 04 <unknown>
+
+sqdecb x0, vl256
+// CHECK-INST: sqdecb x0, vl256
+// CHECK-ENCODING: [0xa0,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f9 30 04 <unknown>
+
+sqdecb x0, #14
+// CHECK-INST: sqdecb x0, #14
+// CHECK-ENCODING: [0xc0,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f9 30 04 <unknown>
+
+sqdecb x0, #15
+// CHECK-INST: sqdecb x0, #15
+// CHECK-ENCODING: [0xe0,0xf9,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f9 30 04 <unknown>
+
+sqdecb x0, #16
+// CHECK-INST: sqdecb x0, #16
+// CHECK-ENCODING: [0x00,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fa 30 04 <unknown>
+
+sqdecb x0, #17
+// CHECK-INST: sqdecb x0, #17
+// CHECK-ENCODING: [0x20,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fa 30 04 <unknown>
+
+sqdecb x0, #18
+// CHECK-INST: sqdecb x0, #18
+// CHECK-ENCODING: [0x40,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fa 30 04 <unknown>
+
+sqdecb x0, #19
+// CHECK-INST: sqdecb x0, #19
+// CHECK-ENCODING: [0x60,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fa 30 04 <unknown>
+
+sqdecb x0, #20
+// CHECK-INST: sqdecb x0, #20
+// CHECK-ENCODING: [0x80,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fa 30 04 <unknown>
+
+sqdecb x0, #21
+// CHECK-INST: sqdecb x0, #21
+// CHECK-ENCODING: [0xa0,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fa 30 04 <unknown>
+
+sqdecb x0, #22
+// CHECK-INST: sqdecb x0, #22
+// CHECK-ENCODING: [0xc0,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fa 30 04 <unknown>
+
+sqdecb x0, #23
+// CHECK-INST: sqdecb x0, #23
+// CHECK-ENCODING: [0xe0,0xfa,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fa 30 04 <unknown>
+
+sqdecb x0, #24
+// CHECK-INST: sqdecb x0, #24
+// CHECK-ENCODING: [0x00,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fb 30 04 <unknown>
+
+sqdecb x0, #25
+// CHECK-INST: sqdecb x0, #25
+// CHECK-ENCODING: [0x20,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fb 30 04 <unknown>
+
+sqdecb x0, #26
+// CHECK-INST: sqdecb x0, #26
+// CHECK-ENCODING: [0x40,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fb 30 04 <unknown>
+
+sqdecb x0, #27
+// CHECK-INST: sqdecb x0, #27
+// CHECK-ENCODING: [0x60,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fb 30 04 <unknown>
+
+sqdecb x0, #28
+// CHECK-INST: sqdecb x0, #28
+// CHECK-ENCODING: [0x80,0xfb,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fb 30 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqdecd w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecd w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecd wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecd sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqdecd x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecd x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecd x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecd x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqdecd x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecd x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecd x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecd x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecd x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqdecd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecd.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecd.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecd x0
+// CHECK-INST: sqdecd x0
+// CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb f0 04 <unknown>
+
+sqdecd x0, all
+// CHECK-INST: sqdecd x0
+// CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb f0 04 <unknown>
+
+sqdecd x0, all, mul #1
+// CHECK-INST: sqdecd x0
+// CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb f0 04 <unknown>
+
+sqdecd x0, all, mul #16
+// CHECK-INST: sqdecd x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb ff 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqdecd x0, pow2
+// CHECK-INST: sqdecd x0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 f0 04 <unknown>
+
+sqdecd x0, vl1
+// CHECK-INST: sqdecd x0, vl1
+// CHECK-ENCODING: [0x20,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 f0 04 <unknown>
+
+sqdecd x0, vl2
+// CHECK-INST: sqdecd x0, vl2
+// CHECK-ENCODING: [0x40,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f8 f0 04 <unknown>
+
+sqdecd x0, vl3
+// CHECK-INST: sqdecd x0, vl3
+// CHECK-ENCODING: [0x60,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f8 f0 04 <unknown>
+
+sqdecd x0, vl4
+// CHECK-INST: sqdecd x0, vl4
+// CHECK-ENCODING: [0x80,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f8 f0 04 <unknown>
+
+sqdecd x0, vl5
+// CHECK-INST: sqdecd x0, vl5
+// CHECK-ENCODING: [0xa0,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f8 f0 04 <unknown>
+
+sqdecd x0, vl6
+// CHECK-INST: sqdecd x0, vl6
+// CHECK-ENCODING: [0xc0,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f8 f0 04 <unknown>
+
+sqdecd x0, vl7
+// CHECK-INST: sqdecd x0, vl7
+// CHECK-ENCODING: [0xe0,0xf8,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f8 f0 04 <unknown>
+
+sqdecd x0, vl8
+// CHECK-INST: sqdecd x0, vl8
+// CHECK-ENCODING: [0x00,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f9 f0 04 <unknown>
+
+sqdecd x0, vl16
+// CHECK-INST: sqdecd x0, vl16
+// CHECK-ENCODING: [0x20,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f9 f0 04 <unknown>
+
+sqdecd x0, vl32
+// CHECK-INST: sqdecd x0, vl32
+// CHECK-ENCODING: [0x40,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f9 f0 04 <unknown>
+
+sqdecd x0, vl64
+// CHECK-INST: sqdecd x0, vl64
+// CHECK-ENCODING: [0x60,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f9 f0 04 <unknown>
+
+sqdecd x0, vl128
+// CHECK-INST: sqdecd x0, vl128
+// CHECK-ENCODING: [0x80,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f9 f0 04 <unknown>
+
+sqdecd x0, vl256
+// CHECK-INST: sqdecd x0, vl256
+// CHECK-ENCODING: [0xa0,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f9 f0 04 <unknown>
+
+sqdecd x0, #14
+// CHECK-INST: sqdecd x0, #14
+// CHECK-ENCODING: [0xc0,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f9 f0 04 <unknown>
+
+sqdecd x0, #15
+// CHECK-INST: sqdecd x0, #15
+// CHECK-ENCODING: [0xe0,0xf9,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f9 f0 04 <unknown>
+
+sqdecd x0, #16
+// CHECK-INST: sqdecd x0, #16
+// CHECK-ENCODING: [0x00,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fa f0 04 <unknown>
+
+sqdecd x0, #17
+// CHECK-INST: sqdecd x0, #17
+// CHECK-ENCODING: [0x20,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fa f0 04 <unknown>
+
+sqdecd x0, #18
+// CHECK-INST: sqdecd x0, #18
+// CHECK-ENCODING: [0x40,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fa f0 04 <unknown>
+
+sqdecd x0, #19
+// CHECK-INST: sqdecd x0, #19
+// CHECK-ENCODING: [0x60,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fa f0 04 <unknown>
+
+sqdecd x0, #20
+// CHECK-INST: sqdecd x0, #20
+// CHECK-ENCODING: [0x80,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fa f0 04 <unknown>
+
+sqdecd x0, #21
+// CHECK-INST: sqdecd x0, #21
+// CHECK-ENCODING: [0xa0,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fa f0 04 <unknown>
+
+sqdecd x0, #22
+// CHECK-INST: sqdecd x0, #22
+// CHECK-ENCODING: [0xc0,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fa f0 04 <unknown>
+
+sqdecd x0, #23
+// CHECK-INST: sqdecd x0, #23
+// CHECK-ENCODING: [0xe0,0xfa,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fa f0 04 <unknown>
+
+sqdecd x0, #24
+// CHECK-INST: sqdecd x0, #24
+// CHECK-ENCODING: [0x00,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fb f0 04 <unknown>
+
+sqdecd x0, #25
+// CHECK-INST: sqdecd x0, #25
+// CHECK-ENCODING: [0x20,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fb f0 04 <unknown>
+
+sqdecd x0, #26
+// CHECK-INST: sqdecd x0, #26
+// CHECK-ENCODING: [0x40,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fb f0 04 <unknown>
+
+sqdecd x0, #27
+// CHECK-INST: sqdecd x0, #27
+// CHECK-ENCODING: [0x60,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fb f0 04 <unknown>
+
+sqdecd x0, #28
+// CHECK-INST: sqdecd x0, #28
+// CHECK-ENCODING: [0x80,0xfb,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fb f0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqdech w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdech w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdech wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdech sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqdech x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdech x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdech x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdech x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqdech x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdech x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdech x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdech x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdech x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqdech.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdech.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdech.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdech x0
+// CHECK-INST: sqdech x0
+// CHECK-ENCODING: [0xe0,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 70 04 <unknown>
+
+sqdech x0, all
+// CHECK-INST: sqdech x0
+// CHECK-ENCODING: [0xe0,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 70 04 <unknown>
+
+sqdech x0, all, mul #1
+// CHECK-INST: sqdech x0
+// CHECK-ENCODING: [0xe0,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 70 04 <unknown>
+
+sqdech x0, all, mul #16
+// CHECK-INST: sqdech x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 7f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqdech x0, pow2
+// CHECK-INST: sqdech x0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 70 04 <unknown>
+
+sqdech x0, vl1
+// CHECK-INST: sqdech x0, vl1
+// CHECK-ENCODING: [0x20,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 70 04 <unknown>
+
+sqdech x0, vl2
+// CHECK-INST: sqdech x0, vl2
+// CHECK-ENCODING: [0x40,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f8 70 04 <unknown>
+
+sqdech x0, vl3
+// CHECK-INST: sqdech x0, vl3
+// CHECK-ENCODING: [0x60,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f8 70 04 <unknown>
+
+sqdech x0, vl4
+// CHECK-INST: sqdech x0, vl4
+// CHECK-ENCODING: [0x80,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f8 70 04 <unknown>
+
+sqdech x0, vl5
+// CHECK-INST: sqdech x0, vl5
+// CHECK-ENCODING: [0xa0,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f8 70 04 <unknown>
+
+sqdech x0, vl6
+// CHECK-INST: sqdech x0, vl6
+// CHECK-ENCODING: [0xc0,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f8 70 04 <unknown>
+
+sqdech x0, vl7
+// CHECK-INST: sqdech x0, vl7
+// CHECK-ENCODING: [0xe0,0xf8,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f8 70 04 <unknown>
+
+sqdech x0, vl8
+// CHECK-INST: sqdech x0, vl8
+// CHECK-ENCODING: [0x00,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f9 70 04 <unknown>
+
+sqdech x0, vl16
+// CHECK-INST: sqdech x0, vl16
+// CHECK-ENCODING: [0x20,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f9 70 04 <unknown>
+
+sqdech x0, vl32
+// CHECK-INST: sqdech x0, vl32
+// CHECK-ENCODING: [0x40,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f9 70 04 <unknown>
+
+sqdech x0, vl64
+// CHECK-INST: sqdech x0, vl64
+// CHECK-ENCODING: [0x60,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f9 70 04 <unknown>
+
+sqdech x0, vl128
+// CHECK-INST: sqdech x0, vl128
+// CHECK-ENCODING: [0x80,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f9 70 04 <unknown>
+
+sqdech x0, vl256
+// CHECK-INST: sqdech x0, vl256
+// CHECK-ENCODING: [0xa0,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f9 70 04 <unknown>
+
+sqdech x0, #14
+// CHECK-INST: sqdech x0, #14
+// CHECK-ENCODING: [0xc0,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f9 70 04 <unknown>
+
+sqdech x0, #15
+// CHECK-INST: sqdech x0, #15
+// CHECK-ENCODING: [0xe0,0xf9,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f9 70 04 <unknown>
+
+sqdech x0, #16
+// CHECK-INST: sqdech x0, #16
+// CHECK-ENCODING: [0x00,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fa 70 04 <unknown>
+
+sqdech x0, #17
+// CHECK-INST: sqdech x0, #17
+// CHECK-ENCODING: [0x20,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fa 70 04 <unknown>
+
+sqdech x0, #18
+// CHECK-INST: sqdech x0, #18
+// CHECK-ENCODING: [0x40,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fa 70 04 <unknown>
+
+sqdech x0, #19
+// CHECK-INST: sqdech x0, #19
+// CHECK-ENCODING: [0x60,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fa 70 04 <unknown>
+
+sqdech x0, #20
+// CHECK-INST: sqdech x0, #20
+// CHECK-ENCODING: [0x80,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fa 70 04 <unknown>
+
+sqdech x0, #21
+// CHECK-INST: sqdech x0, #21
+// CHECK-ENCODING: [0xa0,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fa 70 04 <unknown>
+
+sqdech x0, #22
+// CHECK-INST: sqdech x0, #22
+// CHECK-ENCODING: [0xc0,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fa 70 04 <unknown>
+
+sqdech x0, #23
+// CHECK-INST: sqdech x0, #23
+// CHECK-ENCODING: [0xe0,0xfa,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fa 70 04 <unknown>
+
+sqdech x0, #24
+// CHECK-INST: sqdech x0, #24
+// CHECK-ENCODING: [0x00,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fb 70 04 <unknown>
+
+sqdech x0, #25
+// CHECK-INST: sqdech x0, #25
+// CHECK-ENCODING: [0x20,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fb 70 04 <unknown>
+
+sqdech x0, #26
+// CHECK-INST: sqdech x0, #26
+// CHECK-ENCODING: [0x40,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fb 70 04 <unknown>
+
+sqdech x0, #27
+// CHECK-INST: sqdech x0, #27
+// CHECK-ENCODING: [0x60,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fb 70 04 <unknown>
+
+sqdech x0, #28
+// CHECK-INST: sqdech x0, #28
+// CHECK-ENCODING: [0x80,0xfb,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fb 70 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqdecw w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecw w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecw wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecw sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqdecw x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecw x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecw x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqdecw x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqdecw x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecw x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecw x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecw x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecw x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqdecw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecw.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecw x0
+// CHECK-INST: sqdecw x0
+// CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb b0 04 <unknown>
+
+sqdecw x0, all
+// CHECK-INST: sqdecw x0
+// CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb b0 04 <unknown>
+
+sqdecw x0, all, mul #1
+// CHECK-INST: sqdecw x0
+// CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb b0 04 <unknown>
+
+sqdecw x0, all, mul #16
+// CHECK-INST: sqdecw x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb bf 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqdecw x0, pow2
+// CHECK-INST: sqdecw x0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 b0 04 <unknown>
+
+sqdecw x0, vl1
+// CHECK-INST: sqdecw x0, vl1
+// CHECK-ENCODING: [0x20,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 b0 04 <unknown>
+
+sqdecw x0, vl2
+// CHECK-INST: sqdecw x0, vl2
+// CHECK-ENCODING: [0x40,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f8 b0 04 <unknown>
+
+sqdecw x0, vl3
+// CHECK-INST: sqdecw x0, vl3
+// CHECK-ENCODING: [0x60,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f8 b0 04 <unknown>
+
+sqdecw x0, vl4
+// CHECK-INST: sqdecw x0, vl4
+// CHECK-ENCODING: [0x80,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f8 b0 04 <unknown>
+
+sqdecw x0, vl5
+// CHECK-INST: sqdecw x0, vl5
+// CHECK-ENCODING: [0xa0,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f8 b0 04 <unknown>
+
+sqdecw x0, vl6
+// CHECK-INST: sqdecw x0, vl6
+// CHECK-ENCODING: [0xc0,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f8 b0 04 <unknown>
+
+sqdecw x0, vl7
+// CHECK-INST: sqdecw x0, vl7
+// CHECK-ENCODING: [0xe0,0xf8,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f8 b0 04 <unknown>
+
+sqdecw x0, vl8
+// CHECK-INST: sqdecw x0, vl8
+// CHECK-ENCODING: [0x00,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f9 b0 04 <unknown>
+
+sqdecw x0, vl16
+// CHECK-INST: sqdecw x0, vl16
+// CHECK-ENCODING: [0x20,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f9 b0 04 <unknown>
+
+sqdecw x0, vl32
+// CHECK-INST: sqdecw x0, vl32
+// CHECK-ENCODING: [0x40,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f9 b0 04 <unknown>
+
+sqdecw x0, vl64
+// CHECK-INST: sqdecw x0, vl64
+// CHECK-ENCODING: [0x60,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f9 b0 04 <unknown>
+
+sqdecw x0, vl128
+// CHECK-INST: sqdecw x0, vl128
+// CHECK-ENCODING: [0x80,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f9 b0 04 <unknown>
+
+sqdecw x0, vl256
+// CHECK-INST: sqdecw x0, vl256
+// CHECK-ENCODING: [0xa0,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f9 b0 04 <unknown>
+
+sqdecw x0, #14
+// CHECK-INST: sqdecw x0, #14
+// CHECK-ENCODING: [0xc0,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f9 b0 04 <unknown>
+
+sqdecw x0, #15
+// CHECK-INST: sqdecw x0, #15
+// CHECK-ENCODING: [0xe0,0xf9,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f9 b0 04 <unknown>
+
+sqdecw x0, #16
+// CHECK-INST: sqdecw x0, #16
+// CHECK-ENCODING: [0x00,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fa b0 04 <unknown>
+
+sqdecw x0, #17
+// CHECK-INST: sqdecw x0, #17
+// CHECK-ENCODING: [0x20,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fa b0 04 <unknown>
+
+sqdecw x0, #18
+// CHECK-INST: sqdecw x0, #18
+// CHECK-ENCODING: [0x40,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fa b0 04 <unknown>
+
+sqdecw x0, #19
+// CHECK-INST: sqdecw x0, #19
+// CHECK-ENCODING: [0x60,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fa b0 04 <unknown>
+
+sqdecw x0, #20
+// CHECK-INST: sqdecw x0, #20
+// CHECK-ENCODING: [0x80,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fa b0 04 <unknown>
+
+sqdecw x0, #21
+// CHECK-INST: sqdecw x0, #21
+// CHECK-ENCODING: [0xa0,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fa b0 04 <unknown>
+
+sqdecw x0, #22
+// CHECK-INST: sqdecw x0, #22
+// CHECK-ENCODING: [0xc0,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fa b0 04 <unknown>
+
+sqdecw x0, #23
+// CHECK-INST: sqdecw x0, #23
+// CHECK-ENCODING: [0xe0,0xfa,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fa b0 04 <unknown>
+
+sqdecw x0, #24
+// CHECK-INST: sqdecw x0, #24
+// CHECK-ENCODING: [0x00,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fb b0 04 <unknown>
+
+sqdecw x0, #25
+// CHECK-INST: sqdecw x0, #25
+// CHECK-ENCODING: [0x20,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fb b0 04 <unknown>
+
+sqdecw x0, #26
+// CHECK-INST: sqdecw x0, #26
+// CHECK-ENCODING: [0x40,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fb b0 04 <unknown>
+
+sqdecw x0, #27
+// CHECK-INST: sqdecw x0, #27
+// CHECK-ENCODING: [0x60,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fb b0 04 <unknown>
+
+sqdecw x0, #28
+// CHECK-INST: sqdecw x0, #28
+// CHECK-ENCODING: [0x80,0xfb,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fb b0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqincb w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincb w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincb wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincb sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqincb x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincb x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincb x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincb x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqincb x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincb x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincb x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincb x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincb x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqincb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincb.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,216 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincb x0
+// CHECK-INST: sqincb x0
+// CHECK-ENCODING: [0xe0,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 30 04 <unknown>
+
+sqincb x0, all
+// CHECK-INST: sqincb x0
+// CHECK-ENCODING: [0xe0,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 30 04 <unknown>
+
+sqincb x0, all, mul #1
+// CHECK-INST: sqincb x0
+// CHECK-ENCODING: [0xe0,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 30 04 <unknown>
+
+sqincb x0, all, mul #16
+// CHECK-INST: sqincb x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 3f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqincb x0, pow2
+// CHECK-INST: sqincb x0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 30 04 <unknown>
+
+sqincb x0, vl1
+// CHECK-INST: sqincb x0, vl1
+// CHECK-ENCODING: [0x20,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f0 30 04 <unknown>
+
+sqincb x0, vl2
+// CHECK-INST: sqincb x0, vl2
+// CHECK-ENCODING: [0x40,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f0 30 04 <unknown>
+
+sqincb x0, vl3
+// CHECK-INST: sqincb x0, vl3
+// CHECK-ENCODING: [0x60,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f0 30 04 <unknown>
+
+sqincb x0, vl4
+// CHECK-INST: sqincb x0, vl4
+// CHECK-ENCODING: [0x80,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f0 30 04 <unknown>
+
+sqincb x0, vl5
+// CHECK-INST: sqincb x0, vl5
+// CHECK-ENCODING: [0xa0,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f0 30 04 <unknown>
+
+sqincb x0, vl6
+// CHECK-INST: sqincb x0, vl6
+// CHECK-ENCODING: [0xc0,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f0 30 04 <unknown>
+
+sqincb x0, vl7
+// CHECK-INST: sqincb x0, vl7
+// CHECK-ENCODING: [0xe0,0xf0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f0 30 04 <unknown>
+
+sqincb x0, vl8
+// CHECK-INST: sqincb x0, vl8
+// CHECK-ENCODING: [0x00,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f1 30 04 <unknown>
+
+sqincb x0, vl16
+// CHECK-INST: sqincb x0, vl16
+// CHECK-ENCODING: [0x20,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f1 30 04 <unknown>
+
+sqincb x0, vl32
+// CHECK-INST: sqincb x0, vl32
+// CHECK-ENCODING: [0x40,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f1 30 04 <unknown>
+
+sqincb x0, vl64
+// CHECK-INST: sqincb x0, vl64
+// CHECK-ENCODING: [0x60,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f1 30 04 <unknown>
+
+sqincb x0, vl128
+// CHECK-INST: sqincb x0, vl128
+// CHECK-ENCODING: [0x80,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f1 30 04 <unknown>
+
+sqincb x0, vl256
+// CHECK-INST: sqincb x0, vl256
+// CHECK-ENCODING: [0xa0,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f1 30 04 <unknown>
+
+sqincb x0, #14
+// CHECK-INST: sqincb x0, #14
+// CHECK-ENCODING: [0xc0,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f1 30 04 <unknown>
+
+sqincb x0, #15
+// CHECK-INST: sqincb x0, #15
+// CHECK-ENCODING: [0xe0,0xf1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f1 30 04 <unknown>
+
+sqincb x0, #16
+// CHECK-INST: sqincb x0, #16
+// CHECK-ENCODING: [0x00,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f2 30 04 <unknown>
+
+sqincb x0, #17
+// CHECK-INST: sqincb x0, #17
+// CHECK-ENCODING: [0x20,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f2 30 04 <unknown>
+
+sqincb x0, #18
+// CHECK-INST: sqincb x0, #18
+// CHECK-ENCODING: [0x40,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f2 30 04 <unknown>
+
+sqincb x0, #19
+// CHECK-INST: sqincb x0, #19
+// CHECK-ENCODING: [0x60,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f2 30 04 <unknown>
+
+sqincb x0, #20
+// CHECK-INST: sqincb x0, #20
+// CHECK-ENCODING: [0x80,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f2 30 04 <unknown>
+
+sqincb x0, #21
+// CHECK-INST: sqincb x0, #21
+// CHECK-ENCODING: [0xa0,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f2 30 04 <unknown>
+
+sqincb x0, #22
+// CHECK-INST: sqincb x0, #22
+// CHECK-ENCODING: [0xc0,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f2 30 04 <unknown>
+
+sqincb x0, #23
+// CHECK-INST: sqincb x0, #23
+// CHECK-ENCODING: [0xe0,0xf2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f2 30 04 <unknown>
+
+sqincb x0, #24
+// CHECK-INST: sqincb x0, #24
+// CHECK-ENCODING: [0x00,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f3 30 04 <unknown>
+
+sqincb x0, #25
+// CHECK-INST: sqincb x0, #25
+// CHECK-ENCODING: [0x20,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f3 30 04 <unknown>
+
+sqincb x0, #26
+// CHECK-INST: sqincb x0, #26
+// CHECK-ENCODING: [0x40,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f3 30 04 <unknown>
+
+sqincb x0, #27
+// CHECK-INST: sqincb x0, #27
+// CHECK-ENCODING: [0x60,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f3 30 04 <unknown>
+
+sqincb x0, #28
+// CHECK-INST: sqincb x0, #28
+// CHECK-ENCODING: [0x80,0xf3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f3 30 04 <unknown>
+
Added: llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqincd w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincd w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincd wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincd sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqincd x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincd x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincd x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincd x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqincd x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincd x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincd x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincd x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincd x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqincd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincd.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincd.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincd x0
+// CHECK-INST: sqincd x0
+// CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 f0 04 <unknown>
+
+sqincd x0, all
+// CHECK-INST: sqincd x0
+// CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 f0 04 <unknown>
+
+sqincd x0, all, mul #1
+// CHECK-INST: sqincd x0
+// CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 f0 04 <unknown>
+
+sqincd x0, all, mul #16
+// CHECK-INST: sqincd x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 ff 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqincd x0, pow2
+// CHECK-INST: sqincd x0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 f0 04 <unknown>
+
+sqincd x0, vl1
+// CHECK-INST: sqincd x0, vl1
+// CHECK-ENCODING: [0x20,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f0 f0 04 <unknown>
+
+sqincd x0, vl2
+// CHECK-INST: sqincd x0, vl2
+// CHECK-ENCODING: [0x40,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f0 f0 04 <unknown>
+
+sqincd x0, vl3
+// CHECK-INST: sqincd x0, vl3
+// CHECK-ENCODING: [0x60,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f0 f0 04 <unknown>
+
+sqincd x0, vl4
+// CHECK-INST: sqincd x0, vl4
+// CHECK-ENCODING: [0x80,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f0 f0 04 <unknown>
+
+sqincd x0, vl5
+// CHECK-INST: sqincd x0, vl5
+// CHECK-ENCODING: [0xa0,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f0 f0 04 <unknown>
+
+sqincd x0, vl6
+// CHECK-INST: sqincd x0, vl6
+// CHECK-ENCODING: [0xc0,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f0 f0 04 <unknown>
+
+sqincd x0, vl7
+// CHECK-INST: sqincd x0, vl7
+// CHECK-ENCODING: [0xe0,0xf0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f0 f0 04 <unknown>
+
+sqincd x0, vl8
+// CHECK-INST: sqincd x0, vl8
+// CHECK-ENCODING: [0x00,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f1 f0 04 <unknown>
+
+sqincd x0, vl16
+// CHECK-INST: sqincd x0, vl16
+// CHECK-ENCODING: [0x20,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f1 f0 04 <unknown>
+
+sqincd x0, vl32
+// CHECK-INST: sqincd x0, vl32
+// CHECK-ENCODING: [0x40,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f1 f0 04 <unknown>
+
+sqincd x0, vl64
+// CHECK-INST: sqincd x0, vl64
+// CHECK-ENCODING: [0x60,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f1 f0 04 <unknown>
+
+sqincd x0, vl128
+// CHECK-INST: sqincd x0, vl128
+// CHECK-ENCODING: [0x80,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f1 f0 04 <unknown>
+
+sqincd x0, vl256
+// CHECK-INST: sqincd x0, vl256
+// CHECK-ENCODING: [0xa0,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f1 f0 04 <unknown>
+
+sqincd x0, #14
+// CHECK-INST: sqincd x0, #14
+// CHECK-ENCODING: [0xc0,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f1 f0 04 <unknown>
+
+sqincd x0, #15
+// CHECK-INST: sqincd x0, #15
+// CHECK-ENCODING: [0xe0,0xf1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f1 f0 04 <unknown>
+
+sqincd x0, #16
+// CHECK-INST: sqincd x0, #16
+// CHECK-ENCODING: [0x00,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f2 f0 04 <unknown>
+
+sqincd x0, #17
+// CHECK-INST: sqincd x0, #17
+// CHECK-ENCODING: [0x20,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f2 f0 04 <unknown>
+
+sqincd x0, #18
+// CHECK-INST: sqincd x0, #18
+// CHECK-ENCODING: [0x40,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f2 f0 04 <unknown>
+
+sqincd x0, #19
+// CHECK-INST: sqincd x0, #19
+// CHECK-ENCODING: [0x60,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f2 f0 04 <unknown>
+
+sqincd x0, #20
+// CHECK-INST: sqincd x0, #20
+// CHECK-ENCODING: [0x80,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f2 f0 04 <unknown>
+
+sqincd x0, #21
+// CHECK-INST: sqincd x0, #21
+// CHECK-ENCODING: [0xa0,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f2 f0 04 <unknown>
+
+sqincd x0, #22
+// CHECK-INST: sqincd x0, #22
+// CHECK-ENCODING: [0xc0,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f2 f0 04 <unknown>
+
+sqincd x0, #23
+// CHECK-INST: sqincd x0, #23
+// CHECK-ENCODING: [0xe0,0xf2,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f2 f0 04 <unknown>
+
+sqincd x0, #24
+// CHECK-INST: sqincd x0, #24
+// CHECK-ENCODING: [0x00,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f3 f0 04 <unknown>
+
+sqincd x0, #25
+// CHECK-INST: sqincd x0, #25
+// CHECK-ENCODING: [0x20,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f3 f0 04 <unknown>
+
+sqincd x0, #26
+// CHECK-INST: sqincd x0, #26
+// CHECK-ENCODING: [0x40,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f3 f0 04 <unknown>
+
+sqincd x0, #27
+// CHECK-INST: sqincd x0, #27
+// CHECK-ENCODING: [0x60,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f3 f0 04 <unknown>
+
+sqincd x0, #28
+// CHECK-INST: sqincd x0, #28
+// CHECK-ENCODING: [0x80,0xf3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f3 f0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqinch w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqinch w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqinch wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqinch sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqinch x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqinch x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqinch x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqinch x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqinch x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqinch x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqinch x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqinch x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqinch x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqinch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqinch.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqinch.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqinch x0
+// CHECK-INST: sqinch x0
+// CHECK-ENCODING: [0xe0,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 70 04 <unknown>
+
+sqinch x0, all
+// CHECK-INST: sqinch x0
+// CHECK-ENCODING: [0xe0,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 70 04 <unknown>
+
+sqinch x0, all, mul #1
+// CHECK-INST: sqinch x0
+// CHECK-ENCODING: [0xe0,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 70 04 <unknown>
+
+sqinch x0, all, mul #16
+// CHECK-INST: sqinch x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 7f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqinch x0, pow2
+// CHECK-INST: sqinch x0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 70 04 <unknown>
+
+sqinch x0, vl1
+// CHECK-INST: sqinch x0, vl1
+// CHECK-ENCODING: [0x20,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f0 70 04 <unknown>
+
+sqinch x0, vl2
+// CHECK-INST: sqinch x0, vl2
+// CHECK-ENCODING: [0x40,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f0 70 04 <unknown>
+
+sqinch x0, vl3
+// CHECK-INST: sqinch x0, vl3
+// CHECK-ENCODING: [0x60,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f0 70 04 <unknown>
+
+sqinch x0, vl4
+// CHECK-INST: sqinch x0, vl4
+// CHECK-ENCODING: [0x80,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f0 70 04 <unknown>
+
+sqinch x0, vl5
+// CHECK-INST: sqinch x0, vl5
+// CHECK-ENCODING: [0xa0,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f0 70 04 <unknown>
+
+sqinch x0, vl6
+// CHECK-INST: sqinch x0, vl6
+// CHECK-ENCODING: [0xc0,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f0 70 04 <unknown>
+
+sqinch x0, vl7
+// CHECK-INST: sqinch x0, vl7
+// CHECK-ENCODING: [0xe0,0xf0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f0 70 04 <unknown>
+
+sqinch x0, vl8
+// CHECK-INST: sqinch x0, vl8
+// CHECK-ENCODING: [0x00,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f1 70 04 <unknown>
+
+sqinch x0, vl16
+// CHECK-INST: sqinch x0, vl16
+// CHECK-ENCODING: [0x20,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f1 70 04 <unknown>
+
+sqinch x0, vl32
+// CHECK-INST: sqinch x0, vl32
+// CHECK-ENCODING: [0x40,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f1 70 04 <unknown>
+
+sqinch x0, vl64
+// CHECK-INST: sqinch x0, vl64
+// CHECK-ENCODING: [0x60,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f1 70 04 <unknown>
+
+sqinch x0, vl128
+// CHECK-INST: sqinch x0, vl128
+// CHECK-ENCODING: [0x80,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f1 70 04 <unknown>
+
+sqinch x0, vl256
+// CHECK-INST: sqinch x0, vl256
+// CHECK-ENCODING: [0xa0,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f1 70 04 <unknown>
+
+sqinch x0, #14
+// CHECK-INST: sqinch x0, #14
+// CHECK-ENCODING: [0xc0,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f1 70 04 <unknown>
+
+sqinch x0, #15
+// CHECK-INST: sqinch x0, #15
+// CHECK-ENCODING: [0xe0,0xf1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f1 70 04 <unknown>
+
+sqinch x0, #16
+// CHECK-INST: sqinch x0, #16
+// CHECK-ENCODING: [0x00,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f2 70 04 <unknown>
+
+sqinch x0, #17
+// CHECK-INST: sqinch x0, #17
+// CHECK-ENCODING: [0x20,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f2 70 04 <unknown>
+
+sqinch x0, #18
+// CHECK-INST: sqinch x0, #18
+// CHECK-ENCODING: [0x40,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f2 70 04 <unknown>
+
+sqinch x0, #19
+// CHECK-INST: sqinch x0, #19
+// CHECK-ENCODING: [0x60,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f2 70 04 <unknown>
+
+sqinch x0, #20
+// CHECK-INST: sqinch x0, #20
+// CHECK-ENCODING: [0x80,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f2 70 04 <unknown>
+
+sqinch x0, #21
+// CHECK-INST: sqinch x0, #21
+// CHECK-ENCODING: [0xa0,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f2 70 04 <unknown>
+
+sqinch x0, #22
+// CHECK-INST: sqinch x0, #22
+// CHECK-ENCODING: [0xc0,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f2 70 04 <unknown>
+
+sqinch x0, #23
+// CHECK-INST: sqinch x0, #23
+// CHECK-ENCODING: [0xe0,0xf2,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f2 70 04 <unknown>
+
+sqinch x0, #24
+// CHECK-INST: sqinch x0, #24
+// CHECK-ENCODING: [0x00,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f3 70 04 <unknown>
+
+sqinch x0, #25
+// CHECK-INST: sqinch x0, #25
+// CHECK-ENCODING: [0x20,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f3 70 04 <unknown>
+
+sqinch x0, #26
+// CHECK-INST: sqinch x0, #26
+// CHECK-ENCODING: [0x40,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f3 70 04 <unknown>
+
+sqinch x0, #27
+// CHECK-INST: sqinch x0, #27
+// CHECK-ENCODING: [0x60,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f3 70 04 <unknown>
+
+sqinch x0, #28
+// CHECK-INST: sqinch x0, #28
+// CHECK-ENCODING: [0x80,0xf3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f3 70 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+sqincw w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincw w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincw wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincw sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+sqincw x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincw x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincw x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sqincw x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+sqincw x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincw x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincw x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincw x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincw x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sqincw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincw.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincw x0
+// CHECK-INST: sqincw x0
+// CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
+
+sqincw x0, all
+// CHECK-INST: sqincw x0
+// CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
+
+sqincw x0, all, mul #1
+// CHECK-INST: sqincw x0
+// CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
+
+sqincw x0, all, mul #16
+// CHECK-INST: sqincw x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 bf 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+sqincw x0, pow2
+// CHECK-INST: sqincw x0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 b0 04 <unknown>
+
+sqincw x0, vl1
+// CHECK-INST: sqincw x0, vl1
+// CHECK-ENCODING: [0x20,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f0 b0 04 <unknown>
+
+sqincw x0, vl2
+// CHECK-INST: sqincw x0, vl2
+// CHECK-ENCODING: [0x40,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f0 b0 04 <unknown>
+
+sqincw x0, vl3
+// CHECK-INST: sqincw x0, vl3
+// CHECK-ENCODING: [0x60,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f0 b0 04 <unknown>
+
+sqincw x0, vl4
+// CHECK-INST: sqincw x0, vl4
+// CHECK-ENCODING: [0x80,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f0 b0 04 <unknown>
+
+sqincw x0, vl5
+// CHECK-INST: sqincw x0, vl5
+// CHECK-ENCODING: [0xa0,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f0 b0 04 <unknown>
+
+sqincw x0, vl6
+// CHECK-INST: sqincw x0, vl6
+// CHECK-ENCODING: [0xc0,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f0 b0 04 <unknown>
+
+sqincw x0, vl7
+// CHECK-INST: sqincw x0, vl7
+// CHECK-ENCODING: [0xe0,0xf0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f0 b0 04 <unknown>
+
+sqincw x0, vl8
+// CHECK-INST: sqincw x0, vl8
+// CHECK-ENCODING: [0x00,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f1 b0 04 <unknown>
+
+sqincw x0, vl16
+// CHECK-INST: sqincw x0, vl16
+// CHECK-ENCODING: [0x20,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f1 b0 04 <unknown>
+
+sqincw x0, vl32
+// CHECK-INST: sqincw x0, vl32
+// CHECK-ENCODING: [0x40,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f1 b0 04 <unknown>
+
+sqincw x0, vl64
+// CHECK-INST: sqincw x0, vl64
+// CHECK-ENCODING: [0x60,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f1 b0 04 <unknown>
+
+sqincw x0, vl128
+// CHECK-INST: sqincw x0, vl128
+// CHECK-ENCODING: [0x80,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f1 b0 04 <unknown>
+
+sqincw x0, vl256
+// CHECK-INST: sqincw x0, vl256
+// CHECK-ENCODING: [0xa0,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f1 b0 04 <unknown>
+
+sqincw x0, #14
+// CHECK-INST: sqincw x0, #14
+// CHECK-ENCODING: [0xc0,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f1 b0 04 <unknown>
+
+sqincw x0, #15
+// CHECK-INST: sqincw x0, #15
+// CHECK-ENCODING: [0xe0,0xf1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f1 b0 04 <unknown>
+
+sqincw x0, #16
+// CHECK-INST: sqincw x0, #16
+// CHECK-ENCODING: [0x00,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f2 b0 04 <unknown>
+
+sqincw x0, #17
+// CHECK-INST: sqincw x0, #17
+// CHECK-ENCODING: [0x20,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f2 b0 04 <unknown>
+
+sqincw x0, #18
+// CHECK-INST: sqincw x0, #18
+// CHECK-ENCODING: [0x40,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f2 b0 04 <unknown>
+
+sqincw x0, #19
+// CHECK-INST: sqincw x0, #19
+// CHECK-ENCODING: [0x60,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f2 b0 04 <unknown>
+
+sqincw x0, #20
+// CHECK-INST: sqincw x0, #20
+// CHECK-ENCODING: [0x80,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f2 b0 04 <unknown>
+
+sqincw x0, #21
+// CHECK-INST: sqincw x0, #21
+// CHECK-ENCODING: [0xa0,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f2 b0 04 <unknown>
+
+sqincw x0, #22
+// CHECK-INST: sqincw x0, #22
+// CHECK-ENCODING: [0xc0,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f2 b0 04 <unknown>
+
+sqincw x0, #23
+// CHECK-INST: sqincw x0, #23
+// CHECK-ENCODING: [0xe0,0xf2,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f2 b0 04 <unknown>
+
+sqincw x0, #24
+// CHECK-INST: sqincw x0, #24
+// CHECK-ENCODING: [0x00,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f3 b0 04 <unknown>
+
+sqincw x0, #25
+// CHECK-INST: sqincw x0, #25
+// CHECK-ENCODING: [0x20,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f3 b0 04 <unknown>
+
+sqincw x0, #26
+// CHECK-INST: sqincw x0, #26
+// CHECK-ENCODING: [0x40,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f3 b0 04 <unknown>
+
+sqincw x0, #27
+// CHECK-INST: sqincw x0, #27
+// CHECK-ENCODING: [0x60,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f3 b0 04 <unknown>
+
+sqincw x0, #28
+// CHECK-INST: sqincw x0, #28
+// CHECK-ENCODING: [0x80,0xf3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f3 b0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqdecb w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecb w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecb wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecb sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqdecb x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecb x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecb x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecb x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqdecb x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqdecb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecb.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqdecb x0
+// CHECK-INST: uqdecb x0
+// CHECK-ENCODING: [0xe0,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 30 04 <unknown>
+
+uqdecb x0, all
+// CHECK-INST: uqdecb x0
+// CHECK-ENCODING: [0xe0,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 30 04 <unknown>
+
+uqdecb x0, all, mul #1
+// CHECK-INST: uqdecb x0
+// CHECK-ENCODING: [0xe0,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 30 04 <unknown>
+
+uqdecb x0, all, mul #16
+// CHECK-INST: uqdecb x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 3f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqdecb x0, pow2
+// CHECK-INST: uqdecb x0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 30 04 <unknown>
+
+uqdecb x0, vl1
+// CHECK-INST: uqdecb x0, vl1
+// CHECK-ENCODING: [0x20,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc 30 04 <unknown>
+
+uqdecb x0, vl2
+// CHECK-INST: uqdecb x0, vl2
+// CHECK-ENCODING: [0x40,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fc 30 04 <unknown>
+
+uqdecb x0, vl3
+// CHECK-INST: uqdecb x0, vl3
+// CHECK-ENCODING: [0x60,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fc 30 04 <unknown>
+
+uqdecb x0, vl4
+// CHECK-INST: uqdecb x0, vl4
+// CHECK-ENCODING: [0x80,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fc 30 04 <unknown>
+
+uqdecb x0, vl5
+// CHECK-INST: uqdecb x0, vl5
+// CHECK-ENCODING: [0xa0,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fc 30 04 <unknown>
+
+uqdecb x0, vl6
+// CHECK-INST: uqdecb x0, vl6
+// CHECK-ENCODING: [0xc0,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fc 30 04 <unknown>
+
+uqdecb x0, vl7
+// CHECK-INST: uqdecb x0, vl7
+// CHECK-ENCODING: [0xe0,0xfc,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fc 30 04 <unknown>
+
+uqdecb x0, vl8
+// CHECK-INST: uqdecb x0, vl8
+// CHECK-ENCODING: [0x00,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fd 30 04 <unknown>
+
+uqdecb x0, vl16
+// CHECK-INST: uqdecb x0, vl16
+// CHECK-ENCODING: [0x20,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fd 30 04 <unknown>
+
+uqdecb x0, vl32
+// CHECK-INST: uqdecb x0, vl32
+// CHECK-ENCODING: [0x40,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fd 30 04 <unknown>
+
+uqdecb x0, vl64
+// CHECK-INST: uqdecb x0, vl64
+// CHECK-ENCODING: [0x60,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fd 30 04 <unknown>
+
+uqdecb x0, vl128
+// CHECK-INST: uqdecb x0, vl128
+// CHECK-ENCODING: [0x80,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fd 30 04 <unknown>
+
+uqdecb x0, vl256
+// CHECK-INST: uqdecb x0, vl256
+// CHECK-ENCODING: [0xa0,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fd 30 04 <unknown>
+
+uqdecb x0, #14
+// CHECK-INST: uqdecb x0, #14
+// CHECK-ENCODING: [0xc0,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fd 30 04 <unknown>
+
+uqdecb x0, #15
+// CHECK-INST: uqdecb x0, #15
+// CHECK-ENCODING: [0xe0,0xfd,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fd 30 04 <unknown>
+
+uqdecb x0, #16
+// CHECK-INST: uqdecb x0, #16
+// CHECK-ENCODING: [0x00,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fe 30 04 <unknown>
+
+uqdecb x0, #17
+// CHECK-INST: uqdecb x0, #17
+// CHECK-ENCODING: [0x20,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fe 30 04 <unknown>
+
+uqdecb x0, #18
+// CHECK-INST: uqdecb x0, #18
+// CHECK-ENCODING: [0x40,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fe 30 04 <unknown>
+
+uqdecb x0, #19
+// CHECK-INST: uqdecb x0, #19
+// CHECK-ENCODING: [0x60,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fe 30 04 <unknown>
+
+uqdecb x0, #20
+// CHECK-INST: uqdecb x0, #20
+// CHECK-ENCODING: [0x80,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fe 30 04 <unknown>
+
+uqdecb x0, #21
+// CHECK-INST: uqdecb x0, #21
+// CHECK-ENCODING: [0xa0,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fe 30 04 <unknown>
+
+uqdecb x0, #22
+// CHECK-INST: uqdecb x0, #22
+// CHECK-ENCODING: [0xc0,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fe 30 04 <unknown>
+
+uqdecb x0, #23
+// CHECK-INST: uqdecb x0, #23
+// CHECK-ENCODING: [0xe0,0xfe,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fe 30 04 <unknown>
+
+uqdecb x0, #24
+// CHECK-INST: uqdecb x0, #24
+// CHECK-ENCODING: [0x00,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 ff 30 04 <unknown>
+
+uqdecb x0, #25
+// CHECK-INST: uqdecb x0, #25
+// CHECK-ENCODING: [0x20,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 ff 30 04 <unknown>
+
+uqdecb x0, #26
+// CHECK-INST: uqdecb x0, #26
+// CHECK-ENCODING: [0x40,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 ff 30 04 <unknown>
+
+uqdecb x0, #27
+// CHECK-INST: uqdecb x0, #27
+// CHECK-ENCODING: [0x60,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 ff 30 04 <unknown>
+
+uqdecb x0, #28
+// CHECK-INST: uqdecb x0, #28
+// CHECK-ENCODING: [0x80,0xff,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 ff 30 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqdecd w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecd w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecd wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecd sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqdecd x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecd x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecd x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecd x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqdecd x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqdecd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecd.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecd.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqdecd x0
+// CHECK-INST: uqdecd x0
+// CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff f0 04 <unknown>
+
+uqdecd x0, all
+// CHECK-INST: uqdecd x0
+// CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff f0 04 <unknown>
+
+uqdecd x0, all, mul #1
+// CHECK-INST: uqdecd x0
+// CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff f0 04 <unknown>
+
+uqdecd x0, all, mul #16
+// CHECK-INST: uqdecd x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff ff 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqdecd x0, pow2
+// CHECK-INST: uqdecd x0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc f0 04 <unknown>
+
+uqdecd x0, vl1
+// CHECK-INST: uqdecd x0, vl1
+// CHECK-ENCODING: [0x20,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc f0 04 <unknown>
+
+uqdecd x0, vl2
+// CHECK-INST: uqdecd x0, vl2
+// CHECK-ENCODING: [0x40,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fc f0 04 <unknown>
+
+uqdecd x0, vl3
+// CHECK-INST: uqdecd x0, vl3
+// CHECK-ENCODING: [0x60,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fc f0 04 <unknown>
+
+uqdecd x0, vl4
+// CHECK-INST: uqdecd x0, vl4
+// CHECK-ENCODING: [0x80,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fc f0 04 <unknown>
+
+uqdecd x0, vl5
+// CHECK-INST: uqdecd x0, vl5
+// CHECK-ENCODING: [0xa0,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fc f0 04 <unknown>
+
+uqdecd x0, vl6
+// CHECK-INST: uqdecd x0, vl6
+// CHECK-ENCODING: [0xc0,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fc f0 04 <unknown>
+
+uqdecd x0, vl7
+// CHECK-INST: uqdecd x0, vl7
+// CHECK-ENCODING: [0xe0,0xfc,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fc f0 04 <unknown>
+
+uqdecd x0, vl8
+// CHECK-INST: uqdecd x0, vl8
+// CHECK-ENCODING: [0x00,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fd f0 04 <unknown>
+
+uqdecd x0, vl16
+// CHECK-INST: uqdecd x0, vl16
+// CHECK-ENCODING: [0x20,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fd f0 04 <unknown>
+
+uqdecd x0, vl32
+// CHECK-INST: uqdecd x0, vl32
+// CHECK-ENCODING: [0x40,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fd f0 04 <unknown>
+
+uqdecd x0, vl64
+// CHECK-INST: uqdecd x0, vl64
+// CHECK-ENCODING: [0x60,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fd f0 04 <unknown>
+
+uqdecd x0, vl128
+// CHECK-INST: uqdecd x0, vl128
+// CHECK-ENCODING: [0x80,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fd f0 04 <unknown>
+
+uqdecd x0, vl256
+// CHECK-INST: uqdecd x0, vl256
+// CHECK-ENCODING: [0xa0,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fd f0 04 <unknown>
+
+uqdecd x0, #14
+// CHECK-INST: uqdecd x0, #14
+// CHECK-ENCODING: [0xc0,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fd f0 04 <unknown>
+
+uqdecd x0, #15
+// CHECK-INST: uqdecd x0, #15
+// CHECK-ENCODING: [0xe0,0xfd,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fd f0 04 <unknown>
+
+uqdecd x0, #16
+// CHECK-INST: uqdecd x0, #16
+// CHECK-ENCODING: [0x00,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fe f0 04 <unknown>
+
+uqdecd x0, #17
+// CHECK-INST: uqdecd x0, #17
+// CHECK-ENCODING: [0x20,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fe f0 04 <unknown>
+
+uqdecd x0, #18
+// CHECK-INST: uqdecd x0, #18
+// CHECK-ENCODING: [0x40,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fe f0 04 <unknown>
+
+uqdecd x0, #19
+// CHECK-INST: uqdecd x0, #19
+// CHECK-ENCODING: [0x60,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fe f0 04 <unknown>
+
+uqdecd x0, #20
+// CHECK-INST: uqdecd x0, #20
+// CHECK-ENCODING: [0x80,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fe f0 04 <unknown>
+
+uqdecd x0, #21
+// CHECK-INST: uqdecd x0, #21
+// CHECK-ENCODING: [0xa0,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fe f0 04 <unknown>
+
+uqdecd x0, #22
+// CHECK-INST: uqdecd x0, #22
+// CHECK-ENCODING: [0xc0,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fe f0 04 <unknown>
+
+uqdecd x0, #23
+// CHECK-INST: uqdecd x0, #23
+// CHECK-ENCODING: [0xe0,0xfe,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fe f0 04 <unknown>
+
+uqdecd x0, #24
+// CHECK-INST: uqdecd x0, #24
+// CHECK-ENCODING: [0x00,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 ff f0 04 <unknown>
+
+uqdecd x0, #25
+// CHECK-INST: uqdecd x0, #25
+// CHECK-ENCODING: [0x20,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 ff f0 04 <unknown>
+
+uqdecd x0, #26
+// CHECK-INST: uqdecd x0, #26
+// CHECK-ENCODING: [0x40,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 ff f0 04 <unknown>
+
+uqdecd x0, #27
+// CHECK-INST: uqdecd x0, #27
+// CHECK-ENCODING: [0x60,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 ff f0 04 <unknown>
+
+uqdecd x0, #28
+// CHECK-INST: uqdecd x0, #28
+// CHECK-ENCODING: [0x80,0xff,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 ff f0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqdech w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdech w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdech wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdech sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqdech x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdech x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdech x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdech x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqdech x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqdech.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdech.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdech.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqdech x0
+// CHECK-INST: uqdech x0
+// CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
+
+uqdech x0, all
+// CHECK-INST: uqdech x0
+// CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
+
+uqdech x0, all, mul #1
+// CHECK-INST: uqdech x0
+// CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
+
+uqdech x0, all, mul #16
+// CHECK-INST: uqdech x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 7f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqdech x0, pow2
+// CHECK-INST: uqdech x0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 70 04 <unknown>
+
+uqdech x0, vl1
+// CHECK-INST: uqdech x0, vl1
+// CHECK-ENCODING: [0x20,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc 70 04 <unknown>
+
+uqdech x0, vl2
+// CHECK-INST: uqdech x0, vl2
+// CHECK-ENCODING: [0x40,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fc 70 04 <unknown>
+
+uqdech x0, vl3
+// CHECK-INST: uqdech x0, vl3
+// CHECK-ENCODING: [0x60,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fc 70 04 <unknown>
+
+uqdech x0, vl4
+// CHECK-INST: uqdech x0, vl4
+// CHECK-ENCODING: [0x80,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fc 70 04 <unknown>
+
+uqdech x0, vl5
+// CHECK-INST: uqdech x0, vl5
+// CHECK-ENCODING: [0xa0,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fc 70 04 <unknown>
+
+uqdech x0, vl6
+// CHECK-INST: uqdech x0, vl6
+// CHECK-ENCODING: [0xc0,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fc 70 04 <unknown>
+
+uqdech x0, vl7
+// CHECK-INST: uqdech x0, vl7
+// CHECK-ENCODING: [0xe0,0xfc,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fc 70 04 <unknown>
+
+uqdech x0, vl8
+// CHECK-INST: uqdech x0, vl8
+// CHECK-ENCODING: [0x00,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fd 70 04 <unknown>
+
+uqdech x0, vl16
+// CHECK-INST: uqdech x0, vl16
+// CHECK-ENCODING: [0x20,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fd 70 04 <unknown>
+
+uqdech x0, vl32
+// CHECK-INST: uqdech x0, vl32
+// CHECK-ENCODING: [0x40,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fd 70 04 <unknown>
+
+uqdech x0, vl64
+// CHECK-INST: uqdech x0, vl64
+// CHECK-ENCODING: [0x60,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fd 70 04 <unknown>
+
+uqdech x0, vl128
+// CHECK-INST: uqdech x0, vl128
+// CHECK-ENCODING: [0x80,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fd 70 04 <unknown>
+
+uqdech x0, vl256
+// CHECK-INST: uqdech x0, vl256
+// CHECK-ENCODING: [0xa0,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fd 70 04 <unknown>
+
+uqdech x0, #14
+// CHECK-INST: uqdech x0, #14
+// CHECK-ENCODING: [0xc0,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fd 70 04 <unknown>
+
+uqdech x0, #15
+// CHECK-INST: uqdech x0, #15
+// CHECK-ENCODING: [0xe0,0xfd,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fd 70 04 <unknown>
+
+uqdech x0, #16
+// CHECK-INST: uqdech x0, #16
+// CHECK-ENCODING: [0x00,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fe 70 04 <unknown>
+
+uqdech x0, #17
+// CHECK-INST: uqdech x0, #17
+// CHECK-ENCODING: [0x20,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fe 70 04 <unknown>
+
+uqdech x0, #18
+// CHECK-INST: uqdech x0, #18
+// CHECK-ENCODING: [0x40,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fe 70 04 <unknown>
+
+uqdech x0, #19
+// CHECK-INST: uqdech x0, #19
+// CHECK-ENCODING: [0x60,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fe 70 04 <unknown>
+
+uqdech x0, #20
+// CHECK-INST: uqdech x0, #20
+// CHECK-ENCODING: [0x80,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fe 70 04 <unknown>
+
+uqdech x0, #21
+// CHECK-INST: uqdech x0, #21
+// CHECK-ENCODING: [0xa0,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fe 70 04 <unknown>
+
+uqdech x0, #22
+// CHECK-INST: uqdech x0, #22
+// CHECK-ENCODING: [0xc0,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fe 70 04 <unknown>
+
+uqdech x0, #23
+// CHECK-INST: uqdech x0, #23
+// CHECK-ENCODING: [0xe0,0xfe,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fe 70 04 <unknown>
+
+uqdech x0, #24
+// CHECK-INST: uqdech x0, #24
+// CHECK-ENCODING: [0x00,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 ff 70 04 <unknown>
+
+uqdech x0, #25
+// CHECK-INST: uqdech x0, #25
+// CHECK-ENCODING: [0x20,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 ff 70 04 <unknown>
+
+uqdech x0, #26
+// CHECK-INST: uqdech x0, #26
+// CHECK-ENCODING: [0x40,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 ff 70 04 <unknown>
+
+uqdech x0, #27
+// CHECK-INST: uqdech x0, #27
+// CHECK-ENCODING: [0x60,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 ff 70 04 <unknown>
+
+uqdech x0, #28
+// CHECK-INST: uqdech x0, #28
+// CHECK-ENCODING: [0x80,0xff,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 ff 70 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqdecw w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecw w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecw wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecw sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqdecw x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecw x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecw x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqdecw x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqdecw x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqdecw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecw.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqdecw x0
+// CHECK-INST: uqdecw x0
+// CHECK-ENCODING: [0xe0,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff b0 04 <unknown>
+
+uqdecw x0, all
+// CHECK-INST: uqdecw x0
+// CHECK-ENCODING: [0xe0,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff b0 04 <unknown>
+
+uqdecw x0, all, mul #1
+// CHECK-INST: uqdecw x0
+// CHECK-ENCODING: [0xe0,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff b0 04 <unknown>
+
+uqdecw x0, all, mul #16
+// CHECK-INST: uqdecw x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff bf 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqdecw x0, pow2
+// CHECK-INST: uqdecw x0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc b0 04 <unknown>
+
+uqdecw x0, vl1
+// CHECK-INST: uqdecw x0, vl1
+// CHECK-ENCODING: [0x20,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc b0 04 <unknown>
+
+uqdecw x0, vl2
+// CHECK-INST: uqdecw x0, vl2
+// CHECK-ENCODING: [0x40,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fc b0 04 <unknown>
+
+uqdecw x0, vl3
+// CHECK-INST: uqdecw x0, vl3
+// CHECK-ENCODING: [0x60,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fc b0 04 <unknown>
+
+uqdecw x0, vl4
+// CHECK-INST: uqdecw x0, vl4
+// CHECK-ENCODING: [0x80,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fc b0 04 <unknown>
+
+uqdecw x0, vl5
+// CHECK-INST: uqdecw x0, vl5
+// CHECK-ENCODING: [0xa0,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fc b0 04 <unknown>
+
+uqdecw x0, vl6
+// CHECK-INST: uqdecw x0, vl6
+// CHECK-ENCODING: [0xc0,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fc b0 04 <unknown>
+
+uqdecw x0, vl7
+// CHECK-INST: uqdecw x0, vl7
+// CHECK-ENCODING: [0xe0,0xfc,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fc b0 04 <unknown>
+
+uqdecw x0, vl8
+// CHECK-INST: uqdecw x0, vl8
+// CHECK-ENCODING: [0x00,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fd b0 04 <unknown>
+
+uqdecw x0, vl16
+// CHECK-INST: uqdecw x0, vl16
+// CHECK-ENCODING: [0x20,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fd b0 04 <unknown>
+
+uqdecw x0, vl32
+// CHECK-INST: uqdecw x0, vl32
+// CHECK-ENCODING: [0x40,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fd b0 04 <unknown>
+
+uqdecw x0, vl64
+// CHECK-INST: uqdecw x0, vl64
+// CHECK-ENCODING: [0x60,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fd b0 04 <unknown>
+
+uqdecw x0, vl128
+// CHECK-INST: uqdecw x0, vl128
+// CHECK-ENCODING: [0x80,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fd b0 04 <unknown>
+
+uqdecw x0, vl256
+// CHECK-INST: uqdecw x0, vl256
+// CHECK-ENCODING: [0xa0,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fd b0 04 <unknown>
+
+uqdecw x0, #14
+// CHECK-INST: uqdecw x0, #14
+// CHECK-ENCODING: [0xc0,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fd b0 04 <unknown>
+
+uqdecw x0, #15
+// CHECK-INST: uqdecw x0, #15
+// CHECK-ENCODING: [0xe0,0xfd,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fd b0 04 <unknown>
+
+uqdecw x0, #16
+// CHECK-INST: uqdecw x0, #16
+// CHECK-ENCODING: [0x00,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fe b0 04 <unknown>
+
+uqdecw x0, #17
+// CHECK-INST: uqdecw x0, #17
+// CHECK-ENCODING: [0x20,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fe b0 04 <unknown>
+
+uqdecw x0, #18
+// CHECK-INST: uqdecw x0, #18
+// CHECK-ENCODING: [0x40,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 fe b0 04 <unknown>
+
+uqdecw x0, #19
+// CHECK-INST: uqdecw x0, #19
+// CHECK-ENCODING: [0x60,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 fe b0 04 <unknown>
+
+uqdecw x0, #20
+// CHECK-INST: uqdecw x0, #20
+// CHECK-ENCODING: [0x80,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 fe b0 04 <unknown>
+
+uqdecw x0, #21
+// CHECK-INST: uqdecw x0, #21
+// CHECK-ENCODING: [0xa0,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 fe b0 04 <unknown>
+
+uqdecw x0, #22
+// CHECK-INST: uqdecw x0, #22
+// CHECK-ENCODING: [0xc0,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 fe b0 04 <unknown>
+
+uqdecw x0, #23
+// CHECK-INST: uqdecw x0, #23
+// CHECK-ENCODING: [0xe0,0xfe,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fe b0 04 <unknown>
+
+uqdecw x0, #24
+// CHECK-INST: uqdecw x0, #24
+// CHECK-ENCODING: [0x00,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 ff b0 04 <unknown>
+
+uqdecw x0, #25
+// CHECK-INST: uqdecw x0, #25
+// CHECK-ENCODING: [0x20,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 ff b0 04 <unknown>
+
+uqdecw x0, #26
+// CHECK-INST: uqdecw x0, #26
+// CHECK-ENCODING: [0x40,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 ff b0 04 <unknown>
+
+uqdecw x0, #27
+// CHECK-INST: uqdecw x0, #27
+// CHECK-ENCODING: [0x60,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 ff b0 04 <unknown>
+
+uqdecw x0, #28
+// CHECK-INST: uqdecw x0, #28
+// CHECK-ENCODING: [0x80,0xff,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 ff b0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqincb w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincb w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincb wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincb sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqincb x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincb x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincb x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincb x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqincb x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqincb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincb.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqincb x0
+// CHECK-INST: uqincb x0
+// CHECK-ENCODING: [0xe0,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 30 04 <unknown>
+
+uqincb x0, all
+// CHECK-INST: uqincb x0
+// CHECK-ENCODING: [0xe0,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 30 04 <unknown>
+
+uqincb x0, all, mul #1
+// CHECK-INST: uqincb x0
+// CHECK-ENCODING: [0xe0,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 30 04 <unknown>
+
+uqincb x0, all, mul #16
+// CHECK-INST: uqincb x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 3f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqincb x0, pow2
+// CHECK-INST: uqincb x0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 30 04 <unknown>
+
+uqincb x0, vl1
+// CHECK-INST: uqincb x0, vl1
+// CHECK-ENCODING: [0x20,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f4 30 04 <unknown>
+
+uqincb x0, vl2
+// CHECK-INST: uqincb x0, vl2
+// CHECK-ENCODING: [0x40,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f4 30 04 <unknown>
+
+uqincb x0, vl3
+// CHECK-INST: uqincb x0, vl3
+// CHECK-ENCODING: [0x60,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f4 30 04 <unknown>
+
+uqincb x0, vl4
+// CHECK-INST: uqincb x0, vl4
+// CHECK-ENCODING: [0x80,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f4 30 04 <unknown>
+
+uqincb x0, vl5
+// CHECK-INST: uqincb x0, vl5
+// CHECK-ENCODING: [0xa0,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f4 30 04 <unknown>
+
+uqincb x0, vl6
+// CHECK-INST: uqincb x0, vl6
+// CHECK-ENCODING: [0xc0,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f4 30 04 <unknown>
+
+uqincb x0, vl7
+// CHECK-INST: uqincb x0, vl7
+// CHECK-ENCODING: [0xe0,0xf4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f4 30 04 <unknown>
+
+uqincb x0, vl8
+// CHECK-INST: uqincb x0, vl8
+// CHECK-ENCODING: [0x00,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f5 30 04 <unknown>
+
+uqincb x0, vl16
+// CHECK-INST: uqincb x0, vl16
+// CHECK-ENCODING: [0x20,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f5 30 04 <unknown>
+
+uqincb x0, vl32
+// CHECK-INST: uqincb x0, vl32
+// CHECK-ENCODING: [0x40,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f5 30 04 <unknown>
+
+uqincb x0, vl64
+// CHECK-INST: uqincb x0, vl64
+// CHECK-ENCODING: [0x60,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f5 30 04 <unknown>
+
+uqincb x0, vl128
+// CHECK-INST: uqincb x0, vl128
+// CHECK-ENCODING: [0x80,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f5 30 04 <unknown>
+
+uqincb x0, vl256
+// CHECK-INST: uqincb x0, vl256
+// CHECK-ENCODING: [0xa0,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f5 30 04 <unknown>
+
+uqincb x0, #14
+// CHECK-INST: uqincb x0, #14
+// CHECK-ENCODING: [0xc0,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f5 30 04 <unknown>
+
+uqincb x0, #15
+// CHECK-INST: uqincb x0, #15
+// CHECK-ENCODING: [0xe0,0xf5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f5 30 04 <unknown>
+
+uqincb x0, #16
+// CHECK-INST: uqincb x0, #16
+// CHECK-ENCODING: [0x00,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f6 30 04 <unknown>
+
+uqincb x0, #17
+// CHECK-INST: uqincb x0, #17
+// CHECK-ENCODING: [0x20,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f6 30 04 <unknown>
+
+uqincb x0, #18
+// CHECK-INST: uqincb x0, #18
+// CHECK-ENCODING: [0x40,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f6 30 04 <unknown>
+
+uqincb x0, #19
+// CHECK-INST: uqincb x0, #19
+// CHECK-ENCODING: [0x60,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f6 30 04 <unknown>
+
+uqincb x0, #20
+// CHECK-INST: uqincb x0, #20
+// CHECK-ENCODING: [0x80,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f6 30 04 <unknown>
+
+uqincb x0, #21
+// CHECK-INST: uqincb x0, #21
+// CHECK-ENCODING: [0xa0,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f6 30 04 <unknown>
+
+uqincb x0, #22
+// CHECK-INST: uqincb x0, #22
+// CHECK-ENCODING: [0xc0,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f6 30 04 <unknown>
+
+uqincb x0, #23
+// CHECK-INST: uqincb x0, #23
+// CHECK-ENCODING: [0xe0,0xf6,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f6 30 04 <unknown>
+
+uqincb x0, #24
+// CHECK-INST: uqincb x0, #24
+// CHECK-ENCODING: [0x00,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f7 30 04 <unknown>
+
+uqincb x0, #25
+// CHECK-INST: uqincb x0, #25
+// CHECK-ENCODING: [0x20,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f7 30 04 <unknown>
+
+uqincb x0, #26
+// CHECK-INST: uqincb x0, #26
+// CHECK-ENCODING: [0x40,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f7 30 04 <unknown>
+
+uqincb x0, #27
+// CHECK-INST: uqincb x0, #27
+// CHECK-ENCODING: [0x60,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f7 30 04 <unknown>
+
+uqincb x0, #28
+// CHECK-INST: uqincb x0, #28
+// CHECK-ENCODING: [0x80,0xf7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f7 30 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqincd w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincd w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincd wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincd sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqincd x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincd x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincd x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincd x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqincd x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqincd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincd.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincd.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqincd x0
+// CHECK-INST: uqincd x0
+// CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 f0 04 <unknown>
+
+uqincd x0, all
+// CHECK-INST: uqincd x0
+// CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 f0 04 <unknown>
+
+uqincd x0, all, mul #1
+// CHECK-INST: uqincd x0
+// CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 f0 04 <unknown>
+
+uqincd x0, all, mul #16
+// CHECK-INST: uqincd x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 ff 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqincd x0, pow2
+// CHECK-INST: uqincd x0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 f0 04 <unknown>
+
+uqincd x0, vl1
+// CHECK-INST: uqincd x0, vl1
+// CHECK-ENCODING: [0x20,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f4 f0 04 <unknown>
+
+uqincd x0, vl2
+// CHECK-INST: uqincd x0, vl2
+// CHECK-ENCODING: [0x40,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f4 f0 04 <unknown>
+
+uqincd x0, vl3
+// CHECK-INST: uqincd x0, vl3
+// CHECK-ENCODING: [0x60,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f4 f0 04 <unknown>
+
+uqincd x0, vl4
+// CHECK-INST: uqincd x0, vl4
+// CHECK-ENCODING: [0x80,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f4 f0 04 <unknown>
+
+uqincd x0, vl5
+// CHECK-INST: uqincd x0, vl5
+// CHECK-ENCODING: [0xa0,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f4 f0 04 <unknown>
+
+uqincd x0, vl6
+// CHECK-INST: uqincd x0, vl6
+// CHECK-ENCODING: [0xc0,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f4 f0 04 <unknown>
+
+uqincd x0, vl7
+// CHECK-INST: uqincd x0, vl7
+// CHECK-ENCODING: [0xe0,0xf4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f4 f0 04 <unknown>
+
+uqincd x0, vl8
+// CHECK-INST: uqincd x0, vl8
+// CHECK-ENCODING: [0x00,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f5 f0 04 <unknown>
+
+uqincd x0, vl16
+// CHECK-INST: uqincd x0, vl16
+// CHECK-ENCODING: [0x20,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f5 f0 04 <unknown>
+
+uqincd x0, vl32
+// CHECK-INST: uqincd x0, vl32
+// CHECK-ENCODING: [0x40,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f5 f0 04 <unknown>
+
+uqincd x0, vl64
+// CHECK-INST: uqincd x0, vl64
+// CHECK-ENCODING: [0x60,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f5 f0 04 <unknown>
+
+uqincd x0, vl128
+// CHECK-INST: uqincd x0, vl128
+// CHECK-ENCODING: [0x80,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f5 f0 04 <unknown>
+
+uqincd x0, vl256
+// CHECK-INST: uqincd x0, vl256
+// CHECK-ENCODING: [0xa0,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f5 f0 04 <unknown>
+
+uqincd x0, #14
+// CHECK-INST: uqincd x0, #14
+// CHECK-ENCODING: [0xc0,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f5 f0 04 <unknown>
+
+uqincd x0, #15
+// CHECK-INST: uqincd x0, #15
+// CHECK-ENCODING: [0xe0,0xf5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f5 f0 04 <unknown>
+
+uqincd x0, #16
+// CHECK-INST: uqincd x0, #16
+// CHECK-ENCODING: [0x00,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f6 f0 04 <unknown>
+
+uqincd x0, #17
+// CHECK-INST: uqincd x0, #17
+// CHECK-ENCODING: [0x20,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f6 f0 04 <unknown>
+
+uqincd x0, #18
+// CHECK-INST: uqincd x0, #18
+// CHECK-ENCODING: [0x40,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f6 f0 04 <unknown>
+
+uqincd x0, #19
+// CHECK-INST: uqincd x0, #19
+// CHECK-ENCODING: [0x60,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f6 f0 04 <unknown>
+
+uqincd x0, #20
+// CHECK-INST: uqincd x0, #20
+// CHECK-ENCODING: [0x80,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f6 f0 04 <unknown>
+
+uqincd x0, #21
+// CHECK-INST: uqincd x0, #21
+// CHECK-ENCODING: [0xa0,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f6 f0 04 <unknown>
+
+uqincd x0, #22
+// CHECK-INST: uqincd x0, #22
+// CHECK-ENCODING: [0xc0,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f6 f0 04 <unknown>
+
+uqincd x0, #23
+// CHECK-INST: uqincd x0, #23
+// CHECK-ENCODING: [0xe0,0xf6,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f6 f0 04 <unknown>
+
+uqincd x0, #24
+// CHECK-INST: uqincd x0, #24
+// CHECK-ENCODING: [0x00,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f7 f0 04 <unknown>
+
+uqincd x0, #25
+// CHECK-INST: uqincd x0, #25
+// CHECK-ENCODING: [0x20,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f7 f0 04 <unknown>
+
+uqincd x0, #26
+// CHECK-INST: uqincd x0, #26
+// CHECK-ENCODING: [0x40,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f7 f0 04 <unknown>
+
+uqincd x0, #27
+// CHECK-INST: uqincd x0, #27
+// CHECK-ENCODING: [0x60,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f7 f0 04 <unknown>
+
+uqincd x0, #28
+// CHECK-INST: uqincd x0, #28
+// CHECK-ENCODING: [0x80,0xf7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f7 f0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqinch w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqinch w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqinch wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqinch sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqinch x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqinch x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqinch x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqinch x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqinch x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqinch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqinch.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqinch.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqinch x0
+// CHECK-INST: uqinch x0
+// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 70 04 <unknown>
+
+uqinch x0, all
+// CHECK-INST: uqinch x0
+// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 70 04 <unknown>
+
+uqinch x0, all, mul #1
+// CHECK-INST: uqinch x0
+// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 70 04 <unknown>
+
+uqinch x0, all, mul #16
+// CHECK-INST: uqinch x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 7f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqinch x0, pow2
+// CHECK-INST: uqinch x0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 70 04 <unknown>
+
+uqinch x0, vl1
+// CHECK-INST: uqinch x0, vl1
+// CHECK-ENCODING: [0x20,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f4 70 04 <unknown>
+
+uqinch x0, vl2
+// CHECK-INST: uqinch x0, vl2
+// CHECK-ENCODING: [0x40,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f4 70 04 <unknown>
+
+uqinch x0, vl3
+// CHECK-INST: uqinch x0, vl3
+// CHECK-ENCODING: [0x60,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f4 70 04 <unknown>
+
+uqinch x0, vl4
+// CHECK-INST: uqinch x0, vl4
+// CHECK-ENCODING: [0x80,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f4 70 04 <unknown>
+
+uqinch x0, vl5
+// CHECK-INST: uqinch x0, vl5
+// CHECK-ENCODING: [0xa0,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f4 70 04 <unknown>
+
+uqinch x0, vl6
+// CHECK-INST: uqinch x0, vl6
+// CHECK-ENCODING: [0xc0,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f4 70 04 <unknown>
+
+uqinch x0, vl7
+// CHECK-INST: uqinch x0, vl7
+// CHECK-ENCODING: [0xe0,0xf4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f4 70 04 <unknown>
+
+uqinch x0, vl8
+// CHECK-INST: uqinch x0, vl8
+// CHECK-ENCODING: [0x00,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f5 70 04 <unknown>
+
+uqinch x0, vl16
+// CHECK-INST: uqinch x0, vl16
+// CHECK-ENCODING: [0x20,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f5 70 04 <unknown>
+
+uqinch x0, vl32
+// CHECK-INST: uqinch x0, vl32
+// CHECK-ENCODING: [0x40,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f5 70 04 <unknown>
+
+uqinch x0, vl64
+// CHECK-INST: uqinch x0, vl64
+// CHECK-ENCODING: [0x60,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f5 70 04 <unknown>
+
+uqinch x0, vl128
+// CHECK-INST: uqinch x0, vl128
+// CHECK-ENCODING: [0x80,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f5 70 04 <unknown>
+
+uqinch x0, vl256
+// CHECK-INST: uqinch x0, vl256
+// CHECK-ENCODING: [0xa0,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f5 70 04 <unknown>
+
+uqinch x0, #14
+// CHECK-INST: uqinch x0, #14
+// CHECK-ENCODING: [0xc0,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f5 70 04 <unknown>
+
+uqinch x0, #15
+// CHECK-INST: uqinch x0, #15
+// CHECK-ENCODING: [0xe0,0xf5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f5 70 04 <unknown>
+
+uqinch x0, #16
+// CHECK-INST: uqinch x0, #16
+// CHECK-ENCODING: [0x00,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f6 70 04 <unknown>
+
+uqinch x0, #17
+// CHECK-INST: uqinch x0, #17
+// CHECK-ENCODING: [0x20,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f6 70 04 <unknown>
+
+uqinch x0, #18
+// CHECK-INST: uqinch x0, #18
+// CHECK-ENCODING: [0x40,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f6 70 04 <unknown>
+
+uqinch x0, #19
+// CHECK-INST: uqinch x0, #19
+// CHECK-ENCODING: [0x60,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f6 70 04 <unknown>
+
+uqinch x0, #20
+// CHECK-INST: uqinch x0, #20
+// CHECK-ENCODING: [0x80,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f6 70 04 <unknown>
+
+uqinch x0, #21
+// CHECK-INST: uqinch x0, #21
+// CHECK-ENCODING: [0xa0,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f6 70 04 <unknown>
+
+uqinch x0, #22
+// CHECK-INST: uqinch x0, #22
+// CHECK-ENCODING: [0xc0,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f6 70 04 <unknown>
+
+uqinch x0, #23
+// CHECK-INST: uqinch x0, #23
+// CHECK-ENCODING: [0xe0,0xf6,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f6 70 04 <unknown>
+
+uqinch x0, #24
+// CHECK-INST: uqinch x0, #24
+// CHECK-ENCODING: [0x00,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f7 70 04 <unknown>
+
+uqinch x0, #25
+// CHECK-INST: uqinch x0, #25
+// CHECK-ENCODING: [0x20,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f7 70 04 <unknown>
+
+uqinch x0, #26
+// CHECK-INST: uqinch x0, #26
+// CHECK-ENCODING: [0x40,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f7 70 04 <unknown>
+
+uqinch x0, #27
+// CHECK-INST: uqinch x0, #27
+// CHECK-ENCODING: [0x60,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f7 70 04 <unknown>
+
+uqinch x0, #28
+// CHECK-INST: uqinch x0, #28
+// CHECK-ENCODING: [0x80,0xf7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f7 70 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+uqincw w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincw w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw wsp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincw wsp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincw sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+uqincw x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincw x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincw x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: uqincw x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+uqincw x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uqincw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincw.s?rev=334948&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincw.s Mon Jun 18 07:47:52 2018
@@ -0,0 +1,215 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+// ---------------------------------------------------------------------------//
+// Test 64-bit form (x0) and its aliases
+// ---------------------------------------------------------------------------//
+uqincw x0
+// CHECK-INST: uqincw x0
+// CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 b0 04 <unknown>
+
+uqincw x0, all
+// CHECK-INST: uqincw x0
+// CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 b0 04 <unknown>
+
+uqincw x0, all, mul #1
+// CHECK-INST: uqincw x0
+// CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 b0 04 <unknown>
+
+uqincw x0, all, mul #16
+// CHECK-INST: uqincw x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 bf 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test all patterns for 64-bit form
+// ---------------------------------------------------------------------------//
+
+uqincw x0, pow2
+// CHECK-INST: uqincw x0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 b0 04 <unknown>
+
+uqincw x0, vl1
+// CHECK-INST: uqincw x0, vl1
+// CHECK-ENCODING: [0x20,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f4 b0 04 <unknown>
+
+uqincw x0, vl2
+// CHECK-INST: uqincw x0, vl2
+// CHECK-ENCODING: [0x40,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f4 b0 04 <unknown>
+
+uqincw x0, vl3
+// CHECK-INST: uqincw x0, vl3
+// CHECK-ENCODING: [0x60,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f4 b0 04 <unknown>
+
+uqincw x0, vl4
+// CHECK-INST: uqincw x0, vl4
+// CHECK-ENCODING: [0x80,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f4 b0 04 <unknown>
+
+uqincw x0, vl5
+// CHECK-INST: uqincw x0, vl5
+// CHECK-ENCODING: [0xa0,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f4 b0 04 <unknown>
+
+uqincw x0, vl6
+// CHECK-INST: uqincw x0, vl6
+// CHECK-ENCODING: [0xc0,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f4 b0 04 <unknown>
+
+uqincw x0, vl7
+// CHECK-INST: uqincw x0, vl7
+// CHECK-ENCODING: [0xe0,0xf4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f4 b0 04 <unknown>
+
+uqincw x0, vl8
+// CHECK-INST: uqincw x0, vl8
+// CHECK-ENCODING: [0x00,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f5 b0 04 <unknown>
+
+uqincw x0, vl16
+// CHECK-INST: uqincw x0, vl16
+// CHECK-ENCODING: [0x20,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f5 b0 04 <unknown>
+
+uqincw x0, vl32
+// CHECK-INST: uqincw x0, vl32
+// CHECK-ENCODING: [0x40,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f5 b0 04 <unknown>
+
+uqincw x0, vl64
+// CHECK-INST: uqincw x0, vl64
+// CHECK-ENCODING: [0x60,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f5 b0 04 <unknown>
+
+uqincw x0, vl128
+// CHECK-INST: uqincw x0, vl128
+// CHECK-ENCODING: [0x80,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f5 b0 04 <unknown>
+
+uqincw x0, vl256
+// CHECK-INST: uqincw x0, vl256
+// CHECK-ENCODING: [0xa0,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f5 b0 04 <unknown>
+
+uqincw x0, #14
+// CHECK-INST: uqincw x0, #14
+// CHECK-ENCODING: [0xc0,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f5 b0 04 <unknown>
+
+uqincw x0, #15
+// CHECK-INST: uqincw x0, #15
+// CHECK-ENCODING: [0xe0,0xf5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f5 b0 04 <unknown>
+
+uqincw x0, #16
+// CHECK-INST: uqincw x0, #16
+// CHECK-ENCODING: [0x00,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f6 b0 04 <unknown>
+
+uqincw x0, #17
+// CHECK-INST: uqincw x0, #17
+// CHECK-ENCODING: [0x20,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f6 b0 04 <unknown>
+
+uqincw x0, #18
+// CHECK-INST: uqincw x0, #18
+// CHECK-ENCODING: [0x40,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f6 b0 04 <unknown>
+
+uqincw x0, #19
+// CHECK-INST: uqincw x0, #19
+// CHECK-ENCODING: [0x60,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f6 b0 04 <unknown>
+
+uqincw x0, #20
+// CHECK-INST: uqincw x0, #20
+// CHECK-ENCODING: [0x80,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f6 b0 04 <unknown>
+
+uqincw x0, #21
+// CHECK-INST: uqincw x0, #21
+// CHECK-ENCODING: [0xa0,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 f6 b0 04 <unknown>
+
+uqincw x0, #22
+// CHECK-INST: uqincw x0, #22
+// CHECK-ENCODING: [0xc0,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 f6 b0 04 <unknown>
+
+uqincw x0, #23
+// CHECK-INST: uqincw x0, #23
+// CHECK-ENCODING: [0xe0,0xf6,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f6 b0 04 <unknown>
+
+uqincw x0, #24
+// CHECK-INST: uqincw x0, #24
+// CHECK-ENCODING: [0x00,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f7 b0 04 <unknown>
+
+uqincw x0, #25
+// CHECK-INST: uqincw x0, #25
+// CHECK-ENCODING: [0x20,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f7 b0 04 <unknown>
+
+uqincw x0, #26
+// CHECK-INST: uqincw x0, #26
+// CHECK-ENCODING: [0x40,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 f7 b0 04 <unknown>
+
+uqincw x0, #27
+// CHECK-INST: uqincw x0, #27
+// CHECK-ENCODING: [0x60,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 f7 b0 04 <unknown>
+
+uqincw x0, #28
+// CHECK-INST: uqincw x0, #28
+// CHECK-ENCODING: [0x80,0xf7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 f7 b0 04 <unknown>
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