[PATCH] D47637: Check Sched Class tables at generation time
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 18 07:26:52 PDT 2018
lebedev.ri added inline comments.
================
Comment at: utils/TableGen/SubtargetEmitter.cpp:1272-1278
+ return Orig.NumMicroOps == Inst.NumMicroOps &&
+ Orig.BeginGroup == Inst.BeginGroup &&
+ Orig.EndGroup == Inst.EndGroup &&
+ Orig.WriteProcResIdx == Inst.WriteProcResIdx &&
+ Orig.NumWriteProcResEntries == Inst.NumWriteProcResEntries &&
+ Orig.WriteLatencyIdx == Inst.WriteLatencyIdx &&
+ Orig.NumWriteLatencyEntries == Inst.NumWriteLatencyEntries;
----------------
This is conspiciously similar to the `operator==` of `MCSchedClassDesc`.
And is subtly different. This does not look at `ReadAdvanceIdx`, `NumWriteLatencyEntries`.
I would strongly suggest to:
```
bool EqualityCompare(const MCSchedClassDesc &RHS, bool IgnoreReadAdvance = false) const {
return (NumMicroOps == RHS.NumMicroOps && BeginGroup == RHS.BeginGroup &&
EndGroup == RHS.EndGroup && WriteProcResIdx == RHS.WriteProcResIdx &&
NumWriteProcResEntries == RHS.NumWriteProcResEntries &&
WriteLatencyIdx == RHS.WriteLatencyIdx &&
NumWriteLatencyEntries == RHS.NumWriteLatencyEntries) &&
(IgnoreReadAdvance ||
(ReadAdvanceIdx == RHS.ReadAdvanceIdx && NumReadAdvanceEntries == RHS.NumReadAdvanceEntries)));
}
bool operator==(const MCSchedClassDesc &RHS) const {
return EqualityCompare(RHS, /*IgnoreReadAdvance=*/false);
}
...
if (Orig.NumReadAdvanceEntries && !Inst.NumReadAdvanceEntries) {
return EqualityCompare(RHS, /*IgnoreReadAdvance=*/true);
```
https://reviews.llvm.org/D47637
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