[llvm] r334906 - [AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 17 03:48:22 PDT 2018
Author: s.desmalen
Date: Sun Jun 17 03:48:21 2018
New Revision: 334906
URL: http://llvm.org/viewvc/llvm-project?rev=334906&view=rev
Log:
[AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.
This patch adds support for instructions performing bitwise operations
on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and
their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS.
This patch also adds several aliases:
orr p0.b, p1/z, p1.b, p1.b => mov p0.b, p1.b
orrs p0.b, p1/z, p1.b, p1.b => movs p0.b, p1.b
and p0.b, p1/z, p2.b, p2.b => mov p0.b, p1/z, p2.b
ands p0.b, p1/z, p2.b, p2.b => movs p0.b, p1/z, p2.b
eor p0.b, p1/z, p2.b, p1.b => not p0.b, p1/z, p2.b
eors p0.b, p1/z, p2.b, p1.b => nots p0.b, p1/z, p2.b
Added:
llvm/trunk/test/MC/AArch64/SVE/ands-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ands.s
llvm/trunk/test/MC/AArch64/SVE/bics-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/bics.s
llvm/trunk/test/MC/AArch64/SVE/eors-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/eors.s
llvm/trunk/test/MC/AArch64/SVE/movs.s
llvm/trunk/test/MC/AArch64/SVE/nand-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/nand.s
llvm/trunk/test/MC/AArch64/SVE/nands-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/nands.s
llvm/trunk/test/MC/AArch64/SVE/nor-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/nor.s
llvm/trunk/test/MC/AArch64/SVE/nors-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/nors.s
llvm/trunk/test/MC/AArch64/SVE/not.s
llvm/trunk/test/MC/AArch64/SVE/nots.s
llvm/trunk/test/MC/AArch64/SVE/orns-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/orns.s
llvm/trunk/test/MC/AArch64/SVE/orrs-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/orrs.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/and.s
llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/bic.s
llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/eor.s
llvm/trunk/test/MC/AArch64/SVE/mov.s
llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/orn.s
llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/orr.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Sun Jun 17 03:48:21 2018
@@ -60,7 +60,21 @@ let Predicates = [HasSVE] in {
// Select elements from either vector (predicated)
defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
+ def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
+ def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
+ def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">;
def SEL_PPPP : sve_int_pred_log<0b0011, "sel">;
+ def ANDS_PPzPP : sve_int_pred_log<0b0100, "ands">;
+ def BICS_PPzPP : sve_int_pred_log<0b0101, "bics">;
+ def EORS_PPzPP : sve_int_pred_log<0b0110, "eors">;
+ def ORR_PPzPP : sve_int_pred_log<0b1000, "orr">;
+ def ORN_PPzPP : sve_int_pred_log<0b1001, "orn">;
+ def NOR_PPzPP : sve_int_pred_log<0b1010, "nor">;
+ def NAND_PPzPP : sve_int_pred_log<0b1011, "nand">;
+ def ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs">;
+ def ORNS_PPzPP : sve_int_pred_log<0b1101, "orns">;
+ def NORS_PPzPP : sve_int_pred_log<0b1110, "nors">;
+ def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">;
// continuous load with reg+immediate
defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
@@ -511,4 +525,19 @@ let Predicates = [HasSVE] in {
(ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
def : InstAlias<"mov $Pd, $Pg/m, $Pn",
(SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
+ def : InstAlias<"mov $Pd, $Pn",
+ (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
+ def : InstAlias<"mov $Pd, $Pg/z, $Pn",
+ (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
+
+ def : InstAlias<"movs $Pd, $Pn",
+ (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
+ def : InstAlias<"movs $Pd, $Pg/z, $Pn",
+ (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
+
+ def : InstAlias<"not $Pd, $Pg/z, $Pn",
+ (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
+
+ def : InstAlias<"nots $Pd, $Pg/z, $Pn",
+ (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
}
Modified: llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -65,3 +65,30 @@ and z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+and p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: and p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: and p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: and p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+and p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: and p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/and.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/and.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/and.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/and.s Sun Jun 17 03:48:21 2018
@@ -90,3 +90,21 @@ and z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xda,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f da 04 <unknown>
+
+and p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: and p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0x01,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 01 25 <unknown>
+
+and p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: mov p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 25 <unknown>
+
+and p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: mov p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ands-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ands-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ands-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ands-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+ands p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: ands p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ands p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: ands p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ands p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: ands p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+ands p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ands p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ands.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ands.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ands.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ands.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ands p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: ands p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0x41,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 41 25 <unknown>
+
+ands p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: movs p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 25 <unknown>
+
+ands p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: movs p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 4f 25 <unknown>
+
Modified: llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -65,3 +65,30 @@ bic z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+bic p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bic p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bic p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bic p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+bic p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/bic.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/bic.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/bic.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/bic.s Sun Jun 17 03:48:21 2018
@@ -90,3 +90,15 @@ bic z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xdb,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f db 04 <unknown>
+
+bic p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: bic p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d 0f 25 <unknown>
+
+bic p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: bic p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 00 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/bics-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/bics-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/bics-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/bics-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+bics p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bics p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bics p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bics p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bics p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bics p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+bics p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: bics p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/bics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/bics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/bics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/bics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+bics p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: bics p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 40 25 <unknown>
+
+bics p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: bics p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d 4f 25 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -65,3 +65,30 @@ eor z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+eor p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eor p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eor p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eor p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+eor p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: eor p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/eor.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/eor.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/eor.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/eor.s Sun Jun 17 03:48:21 2018
@@ -90,3 +90,21 @@ eor z31.b, p7/m, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x1f,0x19,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f 19 04 <unknown>
+
+eor p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: eor p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x42,0x01,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 01 25 <unknown>
+
+eor p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: not p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 00 25 <unknown>
+
+eor p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: not p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/eors-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/eors-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/eors-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/eors-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+eors p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eors p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eors p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eors p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eors p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eors p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+eors p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: eors p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/eors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/eors.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/eors.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/eors.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+eors p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: eors p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x42,0x41,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 41 25 <unknown>
+
+eors p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nots p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 40 25 <unknown>
+
+eors p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nots p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 4f 25 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/mov.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/mov.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/mov.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/mov.s Sun Jun 17 03:48:21 2018
@@ -636,3 +636,27 @@ mov z31.d, p15/m, z31.d
// CHECK-ENCODING: [0xff,0xff,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff ff 05 <unknown>
+
+mov p0.b, p0.b
+// CHECK-INST: mov p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 25 <unknown>
+
+mov p15.b, p15.b
+// CHECK-INST: mov p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
+
+mov p0.b, p0/z, p0.b
+// CHECK-INST: mov p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 25 <unknown>
+
+mov p15.b, p15/z, p15.b
+// CHECK-INST: mov p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/movs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/movs.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/movs.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/movs.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+movs p0.b, p0.b
+// CHECK-INST: movs p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 25 <unknown>
+
+movs p15.b, p15.b
+// CHECK-INST: movs p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d cf 25 <unknown>
+
+movs p0.b, p0/z, p0.b
+// CHECK-INST: movs p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 25 <unknown>
+
+movs p15.b, p15/z, p15.b
+// CHECK-INST: movs p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 4f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/nand-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nand-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nand-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nand-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nand p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nand p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nand p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nand p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nand p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nand p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nand p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nand p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/nand.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nand.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nand.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nand.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nand p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nand p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x42,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 42 80 25 <unknown>
+
+nand p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nand p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7f,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f 8f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/nands-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nands-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nands-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nands-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nands p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nands p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nands p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nands p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nands p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nands p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nands p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nands p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/nands.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nands.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nands.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nands.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nands p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nands p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x42,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 42 c0 25 <unknown>
+
+nands p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nands p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7f,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f cf 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/nor-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nor-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nor-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nor-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nor p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nor p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nor p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nor p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nor p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nor p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nor p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nor p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/nor.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nor.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nor.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nor.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nor p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nor p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 80 25 <unknown>
+
+nor p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nor p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 8f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/nors-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nors-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nors-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nors-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nors p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nors p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nors p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nors p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nors p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nors p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nors p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nors p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/nors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nors.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nors.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nors.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nors p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nors p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x42,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 c0 25 <unknown>
+
+nors p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nors p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f cf 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/not.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/not.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/not.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/not.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+not p0.b, p0/z, p0.b
+// CHECK-INST: not p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 00 25 <unknown>
+
+not p15.b, p15/z, p15.b
+// CHECK-INST: not p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/nots.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/nots.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/nots.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/nots.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nots p0.b, p0/z, p0.b
+// CHECK-INST: nots p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 40 25 <unknown>
+
+nots p15.b, p15/z, p15.b
+// CHECK-INST: nots p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 4f 25 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -50,3 +50,30 @@ orn z7.d, z8.d, #254
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: orn z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orn p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orn p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orn p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orn p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orn p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/orn.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orn.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orn.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/orn.s Sun Jun 17 03:48:21 2018
@@ -54,3 +54,15 @@ orn z0.d, z0.d, #0x6
// CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
+
+orn p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: orn p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 80 25 <unknown>
+
+orn p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: orn p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d 8f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/orns-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orns-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orns-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/orns-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orns p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orns p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orns p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orns p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orns p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orns p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orns p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orns p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/orns.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orns.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orns.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/orns.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+orns p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: orns p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 c0 25 <unknown>
+
+orns p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: orns p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d cf 25 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -65,3 +65,30 @@ orr z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orr p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orr p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orr p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orr p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orr p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orr p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/orr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orr.s?rev=334906&r1=334905&r2=334906&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orr.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/orr.s Sun Jun 17 03:48:21 2018
@@ -92,3 +92,21 @@ orr z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xd8,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 1f d8 04 <unknown>
+
+orr p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: orr p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0x81,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 81 25 <unknown>
+
+orr p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: mov p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 25 <unknown>
+
+orr p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: mov p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/orrs-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orrs-diagnostics.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orrs-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/orrs-diagnostics.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orrs p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orrs p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orrs p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orrs p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orrs p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orrs p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orrs p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orrs p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/orrs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orrs.s?rev=334906&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orrs.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/orrs.s Sun Jun 17 03:48:21 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+orrs p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: orrs p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0xc1,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c1 25 <unknown>
+
+orrs p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: movs p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 25 <unknown>
+
+orrs p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: movs p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d cf 25 <unknown>
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