[PATCH] D48230: [PredicateInfo] Order instructions in different BBs by DFSNumIn.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

In https://reviews.llvm.org/D48230#1134015, @efriedma wrote:

> > because values have slightly different labels
>
> Not sure you're diagnosing the issue correctly; IR optimizations shouldn't care about the names of instructions/basic blocks, as far as I know.  But in any case, we need to fix this because a bad sort predicate causes undefined behavior.


Yep I think the issue I hit because of this was not related to IR optimization, but something in the strtab generation in codegen.

> Can you think of any way to write a testcase for this?

I suppose I could add a test case which would visit ops in different orders without this patch and add checks to make sure they are visited in the expected order?


https://reviews.llvm.org/D48230