[PATCH] D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Should there be some AVX512VL tests? We don't have any scheduler that can test XOP instructions AFAICT (unless we want to cheat and use SandyBridge in its role as the generic model).



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Comment at: include/llvm/MC/MCInstrAnalysis.h:88
+                                    const MCInst &Inst,
+                                    BitVector &Writes) const;
+
----------------
When is it better to use BitVector vs APInt? I don't have an answer but we're incredibly inconsistent on this!


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Comment at: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:19
+#include "X86BaseInfo.h"
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/Triple.h"
----------------
Include ordering?


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Comment at: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:316
+    bool HasVEXOrEVEX = ((Desc.TSFlags & X86II::EncodingMask) == X86II::VEX ||
+                         (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX);
+
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XOP instructions? I think the TBM instructions that use this encoding will be safe as they are always GR32/GR64.


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Comment at: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:323
+    const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
+    const MCRegisterClass &XMMRC = MRI.getRegClass(X86::VR128RegClassID);
+
----------------
Is this safe for i686 32-bit targets?


https://reviews.llvm.org/D48225