[llvm] r334838 - [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 15 08:47:44 PDT 2018
Author: s.desmalen
Date: Fri Jun 15 08:47:44 2018
New Revision: 334838
URL: http://llvm.org/viewvc/llvm-project?rev=334838&view=rev
Log:
[AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions.
Increment/decrement scalar register by (scaled) element count given by
predicate pattern, e.g. 'incw x0, all, mul #4'.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47713
Added:
llvm/trunk/test/MC/AArch64/SVE/decb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/decb.s
llvm/trunk/test/MC/AArch64/SVE/decd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/decd.s
llvm/trunk/test/MC/AArch64/SVE/dech-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/dech.s
llvm/trunk/test/MC/AArch64/SVE/decw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/decw.s
llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incb.s
llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incd.s
llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/inch.s
llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incw.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=334838&r1=334837&r2=334838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Fri Jun 15 08:47:44 2018
@@ -477,6 +477,15 @@ let Predicates = [HasSVE] in {
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
+ defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">;
+ defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">;
+ defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">;
+ defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">;
+ defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">;
+ defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">;
+ defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">;
+ defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">;
+
defm INDEX_RR : sve_int_index_rr<"index">;
defm INDEX_IR : sve_int_index_ir<"index">;
defm INDEX_RI : sve_int_index_ri<"index">;
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=334838&r1=334837&r2=334838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Fri Jun 15 08:47:44 2018
@@ -88,7 +88,7 @@ private:
bool parseRegister(OperandVector &Operands);
bool parseSymbolicImmVal(const MCExpr *&ImmVal);
bool parseNeonVectorList(OperandVector &Operands);
- bool parseOptionalMulVl(OperandVector &Operands);
+ bool parseOptionalMulOperand(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, bool isCondCode,
bool invertCondCode);
@@ -3199,27 +3199,45 @@ AArch64AsmParser::tryParseGPROperand(Ope
return MatchOperand_Success;
}
-bool AArch64AsmParser::parseOptionalMulVl(OperandVector &Operands) {
+bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
// Some SVE instructions have a decoration after the immediate, i.e.
// "mul vl". We parse them here and add tokens, which must be present in the
// asm string in the tablegen instruction.
+ bool NextIsVL = Parser.getLexer().peekTok().getString().equals_lower("vl");
+ bool NextIsHash = Parser.getLexer().peekTok().is(AsmToken::Hash);
if (!Parser.getTok().getString().equals_lower("mul") ||
- !Parser.getLexer().peekTok().getString().equals_lower("vl"))
+ !(NextIsVL || NextIsHash))
return true;
- SMLoc S = getLoc();
Operands.push_back(
- AArch64Operand::CreateToken("mul", false, S, getContext()));
+ AArch64Operand::CreateToken("mul", false, getLoc(), getContext()));
Parser.Lex(); // Eat the "mul"
- S = getLoc();
- Operands.push_back(
- AArch64Operand::CreateToken("vl", false, S, getContext()));
- Parser.Lex(); // Eat the "vl"
+ if (NextIsVL) {
+ Operands.push_back(
+ AArch64Operand::CreateToken("vl", false, getLoc(), getContext()));
+ Parser.Lex(); // Eat the "vl"
+ return false;
+ }
- return false;
+ if (NextIsHash) {
+ Parser.Lex(); // Eat the #
+ SMLoc S = getLoc();
+
+ // Parse immediate operand.
+ const MCExpr *ImmVal;
+ if (!Parser.parseExpression(ImmVal))
+ if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal)) {
+ Operands.push_back(AArch64Operand::CreateImm(
+ MCConstantExpr::create(MCE->getValue(), getContext()), S, getLoc(),
+ getContext()));
+ return MatchOperand_Success;
+ }
+ }
+
+ return Error(getLoc(), "expected 'vl' or '#<imm>'");
}
/// parseOperand - Parse a arm instruction operand. For now this parses the
@@ -3275,8 +3293,9 @@ bool AArch64AsmParser::parseOperand(Oper
if (!parseRegister(Operands))
return false;
- // See if this is a "mul vl" decoration used by SVE instructions.
- if (!parseOptionalMulVl(Operands))
+ // See if this is a "mul vl" decoration or "mul #<int>" operand used
+ // by SVE instructions.
+ if (!parseOptionalMulOperand(Operands))
return false;
// This could be an optional "shift" or "extend" operand.
Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=334838&r1=334837&r2=334838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Fri Jun 15 08:47:44 2018
@@ -210,6 +210,8 @@ static DecodeStatus DecodeSImm(llvm::MCI
template <int ElementWidth>
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder);
+static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
+ uint64_t Addr, const void *Decoder);
static bool Check(DecodeStatus &Out, DecodeStatus In) {
switch (In) {
@@ -1791,3 +1793,10 @@ static DecodeStatus DecodeImm8OptLsl(MCI
Inst.addOperand(MCOperand::createImm(Shift));
return Success;
}
+
+// Decode uimm4 ranged from 1-16.
+static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
+ uint64_t Addr, const void *Decoder) {
+ Inst.addOperand(MCOperand::createImm(Imm + 1));
+ return Success;
+}
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp?rev=334838&r1=334837&r2=334838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp Fri Jun 15 08:47:44 2018
@@ -166,6 +166,9 @@ public:
uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
@@ -531,6 +534,16 @@ AArch64MCCodeEmitter::getImm8OptLsl(cons
return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal));
}
+uint32_t
+AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpIdx);
+ assert(MO.isImm() && "Expected an immediate value!");
+ // Normalize 1-16 range to 0-15.
+ return MO.getImm() - 1;
+}
+
/// getMoveVecShifterOpValue - Return the encoded value for the vector move
/// shifter (MSL).
uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=334838&r1=334837&r2=334838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Fri Jun 15 08:47:44 2018
@@ -226,6 +226,14 @@ def sve_fpimm_zero_one
: SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero",
"AArch64ExactFPImm::one">;
+def sve_incdec_imm : Operand<i32>, ImmLeaf<i32, [{
+ return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
+}]> {
+ let ParserMatchClass = Imm1_16Operand;
+ let EncoderMethod = "getSVEIncDecImm";
+ let DecoderMethod = "DecodeSVEIncDecImm";
+}
+
//===----------------------------------------------------------------------===//
// SVE PTrue - These are used extensively throughout the pattern matching so
// it's important we define them first.
@@ -272,6 +280,41 @@ let Predicates = [HasSVE] in {
defm PTRUES : sve_int_ptrue<0b001, "ptrues">;
}
+
+//===----------------------------------------------------------------------===//
+// SVE Element Count Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_pred_pattern_a<bits<3> opc, string asm>
+: I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
+ asm, "\t$Rdn, $pattern, mul $imm4",
+ "",
+ []>, Sched<[]> {
+ bits<5> Rdn;
+ bits<5> pattern;
+ bits<4> imm4;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = opc{2-1};
+ let Inst{21-20} = 0b11;
+ let Inst{19-16} = imm4;
+ let Inst{15-11} = 0b11100;
+ let Inst{10} = opc{0};
+ let Inst{9-5} = pattern;
+ let Inst{4-0} = Rdn;
+
+ let Constraints = "$Rdn = $_Rdn";
+}
+
+multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> {
+ def NAME : sve_int_pred_pattern_a<opc, asm>;
+
+ def : InstAlias<asm # "\t$Rdn, $pattern",
+ (!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>;
+ def : InstAlias<asm # "\t$Rdn",
+ (!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
+}
+
+
//===----------------------------------------------------------------------===//
// SVE Permute - Cross Lane Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE/decb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decb-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/decb-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+decb w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: decb w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decb sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: decb sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+decb x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decb x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decb x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decb x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decb x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decb x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+decb x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decb x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decb x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decb x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decb x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decb x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decb x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decb x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/decb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decb.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/decb.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+decb x0
+// CHECK-INST: decb x0
+// CHECK-ENCODING: [0xe0,0xe7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 30 04 <unknown>
+
+decb x0, all
+// CHECK-INST: decb x0
+// CHECK-ENCODING: [0xe0,0xe7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 30 04 <unknown>
+
+decb x0, all, mul #1
+// CHECK-INST: decb x0
+// CHECK-ENCODING: [0xe0,0xe7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 30 04 <unknown>
+
+decb x0, all, mul #16
+// CHECK-INST: decb x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe7,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 3f 04 <unknown>
+
+decb x0, pow2
+// CHECK-INST: decb x0, pow2
+// CHECK-ENCODING: [0x00,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e4 30 04 <unknown>
+
+decb x0, vl1
+// CHECK-INST: decb x0, vl1
+// CHECK-ENCODING: [0x20,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e4 30 04 <unknown>
+
+decb x0, vl2
+// CHECK-INST: decb x0, vl2
+// CHECK-ENCODING: [0x40,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e4 30 04 <unknown>
+
+decb x0, vl3
+// CHECK-INST: decb x0, vl3
+// CHECK-ENCODING: [0x60,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e4 30 04 <unknown>
+
+decb x0, vl4
+// CHECK-INST: decb x0, vl4
+// CHECK-ENCODING: [0x80,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e4 30 04 <unknown>
+
+decb x0, vl5
+// CHECK-INST: decb x0, vl5
+// CHECK-ENCODING: [0xa0,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e4 30 04 <unknown>
+
+decb x0, vl6
+// CHECK-INST: decb x0, vl6
+// CHECK-ENCODING: [0xc0,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e4 30 04 <unknown>
+
+decb x0, vl7
+// CHECK-INST: decb x0, vl7
+// CHECK-ENCODING: [0xe0,0xe4,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e4 30 04 <unknown>
+
+decb x0, vl8
+// CHECK-INST: decb x0, vl8
+// CHECK-ENCODING: [0x00,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e5 30 04 <unknown>
+
+decb x0, vl16
+// CHECK-INST: decb x0, vl16
+// CHECK-ENCODING: [0x20,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e5 30 04 <unknown>
+
+decb x0, vl32
+// CHECK-INST: decb x0, vl32
+// CHECK-ENCODING: [0x40,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e5 30 04 <unknown>
+
+decb x0, vl64
+// CHECK-INST: decb x0, vl64
+// CHECK-ENCODING: [0x60,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e5 30 04 <unknown>
+
+decb x0, vl128
+// CHECK-INST: decb x0, vl128
+// CHECK-ENCODING: [0x80,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e5 30 04 <unknown>
+
+decb x0, vl256
+// CHECK-INST: decb x0, vl256
+// CHECK-ENCODING: [0xa0,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e5 30 04 <unknown>
+
+decb x0, #14
+// CHECK-INST: decb x0, #14
+// CHECK-ENCODING: [0xc0,0xe5,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e5 30 04 <unknown>
+
+decb x0, #28
+// CHECK-INST: decb x0, #28
+// CHECK-ENCODING: [0x80,0xe7,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e7 30 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/decd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decd-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decd-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/decd-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+decd w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: decd w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decd sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: decd sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+decd x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decd x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decd x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decd x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decd x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decd x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+decd x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decd x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decd x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decd x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decd x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decd x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decd x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decd x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/decd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decd.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decd.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/decd.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+decd x0
+// CHECK-INST: decd x0
+// CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 f0 04 <unknown>
+
+decd x0, all
+// CHECK-INST: decd x0
+// CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 f0 04 <unknown>
+
+decd x0, all, mul #1
+// CHECK-INST: decd x0
+// CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 f0 04 <unknown>
+
+decd x0, all, mul #16
+// CHECK-INST: decd x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe7,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 ff 04 <unknown>
+
+decd x0, pow2
+// CHECK-INST: decd x0, pow2
+// CHECK-ENCODING: [0x00,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e4 f0 04 <unknown>
+
+decd x0, vl1
+// CHECK-INST: decd x0, vl1
+// CHECK-ENCODING: [0x20,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e4 f0 04 <unknown>
+
+decd x0, vl2
+// CHECK-INST: decd x0, vl2
+// CHECK-ENCODING: [0x40,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e4 f0 04 <unknown>
+
+decd x0, vl3
+// CHECK-INST: decd x0, vl3
+// CHECK-ENCODING: [0x60,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e4 f0 04 <unknown>
+
+decd x0, vl4
+// CHECK-INST: decd x0, vl4
+// CHECK-ENCODING: [0x80,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e4 f0 04 <unknown>
+
+decd x0, vl5
+// CHECK-INST: decd x0, vl5
+// CHECK-ENCODING: [0xa0,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e4 f0 04 <unknown>
+
+decd x0, vl6
+// CHECK-INST: decd x0, vl6
+// CHECK-ENCODING: [0xc0,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e4 f0 04 <unknown>
+
+decd x0, vl7
+// CHECK-INST: decd x0, vl7
+// CHECK-ENCODING: [0xe0,0xe4,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e4 f0 04 <unknown>
+
+decd x0, vl8
+// CHECK-INST: decd x0, vl8
+// CHECK-ENCODING: [0x00,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e5 f0 04 <unknown>
+
+decd x0, vl16
+// CHECK-INST: decd x0, vl16
+// CHECK-ENCODING: [0x20,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e5 f0 04 <unknown>
+
+decd x0, vl32
+// CHECK-INST: decd x0, vl32
+// CHECK-ENCODING: [0x40,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e5 f0 04 <unknown>
+
+decd x0, vl64
+// CHECK-INST: decd x0, vl64
+// CHECK-ENCODING: [0x60,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e5 f0 04 <unknown>
+
+decd x0, vl128
+// CHECK-INST: decd x0, vl128
+// CHECK-ENCODING: [0x80,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e5 f0 04 <unknown>
+
+decd x0, vl256
+// CHECK-INST: decd x0, vl256
+// CHECK-ENCODING: [0xa0,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e5 f0 04 <unknown>
+
+decd x0, #14
+// CHECK-INST: decd x0, #14
+// CHECK-ENCODING: [0xc0,0xe5,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e5 f0 04 <unknown>
+
+decd x0, #28
+// CHECK-INST: decd x0, #28
+// CHECK-ENCODING: [0x80,0xe7,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e7 f0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/dech-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/dech-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/dech-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/dech-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+dech w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: dech w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dech sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: dech sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+dech x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: dech x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dech x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: dech x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dech x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: dech x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+dech x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: dech x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dech x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: dech x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dech x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: dech x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+dech x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: dech x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/dech.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/dech.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/dech.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/dech.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+dech x0
+// CHECK-INST: dech x0
+// CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
+
+dech x0, all
+// CHECK-INST: dech x0
+// CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
+
+dech x0, all, mul #1
+// CHECK-INST: dech x0
+// CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
+
+dech x0, all, mul #16
+// CHECK-INST: dech x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe7,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 7f 04 <unknown>
+
+dech x0, pow2
+// CHECK-INST: dech x0, pow2
+// CHECK-ENCODING: [0x00,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e4 70 04 <unknown>
+
+dech x0, vl1
+// CHECK-INST: dech x0, vl1
+// CHECK-ENCODING: [0x20,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e4 70 04 <unknown>
+
+dech x0, vl2
+// CHECK-INST: dech x0, vl2
+// CHECK-ENCODING: [0x40,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e4 70 04 <unknown>
+
+dech x0, vl3
+// CHECK-INST: dech x0, vl3
+// CHECK-ENCODING: [0x60,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e4 70 04 <unknown>
+
+dech x0, vl4
+// CHECK-INST: dech x0, vl4
+// CHECK-ENCODING: [0x80,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e4 70 04 <unknown>
+
+dech x0, vl5
+// CHECK-INST: dech x0, vl5
+// CHECK-ENCODING: [0xa0,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e4 70 04 <unknown>
+
+dech x0, vl6
+// CHECK-INST: dech x0, vl6
+// CHECK-ENCODING: [0xc0,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e4 70 04 <unknown>
+
+dech x0, vl7
+// CHECK-INST: dech x0, vl7
+// CHECK-ENCODING: [0xe0,0xe4,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e4 70 04 <unknown>
+
+dech x0, vl8
+// CHECK-INST: dech x0, vl8
+// CHECK-ENCODING: [0x00,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e5 70 04 <unknown>
+
+dech x0, vl16
+// CHECK-INST: dech x0, vl16
+// CHECK-ENCODING: [0x20,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e5 70 04 <unknown>
+
+dech x0, vl32
+// CHECK-INST: dech x0, vl32
+// CHECK-ENCODING: [0x40,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e5 70 04 <unknown>
+
+dech x0, vl64
+// CHECK-INST: dech x0, vl64
+// CHECK-ENCODING: [0x60,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e5 70 04 <unknown>
+
+dech x0, vl128
+// CHECK-INST: dech x0, vl128
+// CHECK-ENCODING: [0x80,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e5 70 04 <unknown>
+
+dech x0, vl256
+// CHECK-INST: dech x0, vl256
+// CHECK-ENCODING: [0xa0,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e5 70 04 <unknown>
+
+dech x0, #14
+// CHECK-INST: dech x0, #14
+// CHECK-ENCODING: [0xc0,0xe5,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e5 70 04 <unknown>
+
+dech x0, #28
+// CHECK-INST: dech x0, #28
+// CHECK-ENCODING: [0x80,0xe7,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e7 70 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/decw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decw-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/decw-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+decw w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: decw w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decw sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: decw sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+decw x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decw x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decw x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decw x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decw x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: decw x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+decw x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decw x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decw x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decw x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decw x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decw x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decw x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: decw x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/decw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decw.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/decw.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+decw x0
+// CHECK-INST: decw x0
+// CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 b0 04 <unknown>
+
+decw x0, all
+// CHECK-INST: decw x0
+// CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 b0 04 <unknown>
+
+decw x0, all, mul #1
+// CHECK-INST: decw x0
+// CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 b0 04 <unknown>
+
+decw x0, all, mul #16
+// CHECK-INST: decw x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe7,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e7 bf 04 <unknown>
+
+decw x0, pow2
+// CHECK-INST: decw x0, pow2
+// CHECK-ENCODING: [0x00,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e4 b0 04 <unknown>
+
+decw x0, vl1
+// CHECK-INST: decw x0, vl1
+// CHECK-ENCODING: [0x20,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e4 b0 04 <unknown>
+
+decw x0, vl2
+// CHECK-INST: decw x0, vl2
+// CHECK-ENCODING: [0x40,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e4 b0 04 <unknown>
+
+decw x0, vl3
+// CHECK-INST: decw x0, vl3
+// CHECK-ENCODING: [0x60,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e4 b0 04 <unknown>
+
+decw x0, vl4
+// CHECK-INST: decw x0, vl4
+// CHECK-ENCODING: [0x80,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e4 b0 04 <unknown>
+
+decw x0, vl5
+// CHECK-INST: decw x0, vl5
+// CHECK-ENCODING: [0xa0,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e4 b0 04 <unknown>
+
+decw x0, vl6
+// CHECK-INST: decw x0, vl6
+// CHECK-ENCODING: [0xc0,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e4 b0 04 <unknown>
+
+decw x0, vl7
+// CHECK-INST: decw x0, vl7
+// CHECK-ENCODING: [0xe0,0xe4,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e4 b0 04 <unknown>
+
+decw x0, vl8
+// CHECK-INST: decw x0, vl8
+// CHECK-ENCODING: [0x00,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e5 b0 04 <unknown>
+
+decw x0, vl16
+// CHECK-INST: decw x0, vl16
+// CHECK-ENCODING: [0x20,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e5 b0 04 <unknown>
+
+decw x0, vl32
+// CHECK-INST: decw x0, vl32
+// CHECK-ENCODING: [0x40,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e5 b0 04 <unknown>
+
+decw x0, vl64
+// CHECK-INST: decw x0, vl64
+// CHECK-ENCODING: [0x60,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e5 b0 04 <unknown>
+
+decw x0, vl128
+// CHECK-INST: decw x0, vl128
+// CHECK-ENCODING: [0x80,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e5 b0 04 <unknown>
+
+decw x0, vl256
+// CHECK-INST: decw x0, vl256
+// CHECK-ENCODING: [0xa0,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e5 b0 04 <unknown>
+
+decw x0, #14
+// CHECK-INST: decw x0, #14
+// CHECK-ENCODING: [0xc0,0xe5,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e5 b0 04 <unknown>
+
+decw x0, #28
+// CHECK-INST: decw x0, #28
+// CHECK-ENCODING: [0x80,0xe7,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e7 b0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+incb w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incb w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incb sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incb sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+incb x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incb x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incb x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incb x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incb x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incb x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+incb x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incb x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incb x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incb x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incb x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incb x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incb x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incb x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/incb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incb.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/incb.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,206 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+incb x0
+// CHECK-INST: incb x0
+// CHECK-ENCODING: [0xe0,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 30 04 <unknown>
+
+incb x0, all
+// CHECK-INST: incb x0
+// CHECK-ENCODING: [0xe0,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 30 04 <unknown>
+
+incb x0, all, mul #1
+// CHECK-INST: incb x0
+// CHECK-ENCODING: [0xe0,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 30 04 <unknown>
+
+incb x0, all, mul #16
+// CHECK-INST: incb x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe3,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 3f 04 <unknown>
+
+incb x0, pow2
+// CHECK-INST: incb x0, pow2
+// CHECK-ENCODING: [0x00,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 30 04 <unknown>
+
+incb x0, vl1
+// CHECK-INST: incb x0, vl1
+// CHECK-ENCODING: [0x20,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e0 30 04 <unknown>
+
+incb x0, vl2
+// CHECK-INST: incb x0, vl2
+// CHECK-ENCODING: [0x40,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e0 30 04 <unknown>
+
+incb x0, vl3
+// CHECK-INST: incb x0, vl3
+// CHECK-ENCODING: [0x60,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e0 30 04 <unknown>
+
+incb x0, vl4
+// CHECK-INST: incb x0, vl4
+// CHECK-ENCODING: [0x80,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e0 30 04 <unknown>
+
+incb x0, vl5
+// CHECK-INST: incb x0, vl5
+// CHECK-ENCODING: [0xa0,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e0 30 04 <unknown>
+
+incb x0, vl6
+// CHECK-INST: incb x0, vl6
+// CHECK-ENCODING: [0xc0,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e0 30 04 <unknown>
+
+incb x0, vl7
+// CHECK-INST: incb x0, vl7
+// CHECK-ENCODING: [0xe0,0xe0,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e0 30 04 <unknown>
+
+incb x0, vl8
+// CHECK-INST: incb x0, vl8
+// CHECK-ENCODING: [0x00,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e1 30 04 <unknown>
+
+incb x0, vl16
+// CHECK-INST: incb x0, vl16
+// CHECK-ENCODING: [0x20,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e1 30 04 <unknown>
+
+incb x0, vl32
+// CHECK-INST: incb x0, vl32
+// CHECK-ENCODING: [0x40,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e1 30 04 <unknown>
+
+incb x0, vl64
+// CHECK-INST: incb x0, vl64
+// CHECK-ENCODING: [0x60,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e1 30 04 <unknown>
+
+incb x0, vl128
+// CHECK-INST: incb x0, vl128
+// CHECK-ENCODING: [0x80,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e1 30 04 <unknown>
+
+incb x0, vl256
+// CHECK-INST: incb x0, vl256
+// CHECK-ENCODING: [0xa0,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e1 30 04 <unknown>
+
+incb x0, #14
+// CHECK-INST: incb x0, #14
+// CHECK-ENCODING: [0xc0,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e1 30 04 <unknown>
+
+incb x0, #15
+// CHECK-INST: incb x0, #15
+// CHECK-ENCODING: [0xe0,0xe1,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e1 30 04 <unknown>
+
+incb x0, #16
+// CHECK-INST: incb x0, #16
+// CHECK-ENCODING: [0x00,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e2 30 04 <unknown>
+
+incb x0, #17
+// CHECK-INST: incb x0, #17
+// CHECK-ENCODING: [0x20,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e2 30 04 <unknown>
+
+incb x0, #18
+// CHECK-INST: incb x0, #18
+// CHECK-ENCODING: [0x40,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e2 30 04 <unknown>
+
+incb x0, #19
+// CHECK-INST: incb x0, #19
+// CHECK-ENCODING: [0x60,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e2 30 04 <unknown>
+
+incb x0, #20
+// CHECK-INST: incb x0, #20
+// CHECK-ENCODING: [0x80,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e2 30 04 <unknown>
+
+incb x0, #21
+// CHECK-INST: incb x0, #21
+// CHECK-ENCODING: [0xa0,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e2 30 04 <unknown>
+
+incb x0, #22
+// CHECK-INST: incb x0, #22
+// CHECK-ENCODING: [0xc0,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e2 30 04 <unknown>
+
+incb x0, #23
+// CHECK-INST: incb x0, #23
+// CHECK-ENCODING: [0xe0,0xe2,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e2 30 04 <unknown>
+
+incb x0, #24
+// CHECK-INST: incb x0, #24
+// CHECK-ENCODING: [0x00,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e3 30 04 <unknown>
+
+incb x0, #25
+// CHECK-INST: incb x0, #25
+// CHECK-ENCODING: [0x20,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e3 30 04 <unknown>
+
+incb x0, #26
+// CHECK-INST: incb x0, #26
+// CHECK-ENCODING: [0x40,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e3 30 04 <unknown>
+
+incb x0, #27
+// CHECK-INST: incb x0, #27
+// CHECK-ENCODING: [0x60,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e3 30 04 <unknown>
+
+incb x0, #28
+// CHECK-INST: incb x0, #28
+// CHECK-ENCODING: [0x80,0xe3,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e3 30 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+incd w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incd w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incd sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incd sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+incd x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incd x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incd x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incd x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incd x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incd x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+incd x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incd x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incd x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incd x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incd x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incd x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incd x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incd x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/incd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incd.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incd.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/incd.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+incd x0
+// CHECK-INST: incd x0
+// CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 f0 04 <unknown>
+
+incd x0, all
+// CHECK-INST: incd x0
+// CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 f0 04 <unknown>
+
+incd x0, all, mul #1
+// CHECK-INST: incd x0
+// CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 f0 04 <unknown>
+
+incd x0, all, mul #16
+// CHECK-INST: incd x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe3,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 ff 04 <unknown>
+
+incd x0, pow2
+// CHECK-INST: incd x0, pow2
+// CHECK-ENCODING: [0x00,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 f0 04 <unknown>
+
+incd x0, vl1
+// CHECK-INST: incd x0, vl1
+// CHECK-ENCODING: [0x20,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e0 f0 04 <unknown>
+
+incd x0, vl2
+// CHECK-INST: incd x0, vl2
+// CHECK-ENCODING: [0x40,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e0 f0 04 <unknown>
+
+incd x0, vl3
+// CHECK-INST: incd x0, vl3
+// CHECK-ENCODING: [0x60,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e0 f0 04 <unknown>
+
+incd x0, vl4
+// CHECK-INST: incd x0, vl4
+// CHECK-ENCODING: [0x80,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e0 f0 04 <unknown>
+
+incd x0, vl5
+// CHECK-INST: incd x0, vl5
+// CHECK-ENCODING: [0xa0,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e0 f0 04 <unknown>
+
+incd x0, vl6
+// CHECK-INST: incd x0, vl6
+// CHECK-ENCODING: [0xc0,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e0 f0 04 <unknown>
+
+incd x0, vl7
+// CHECK-INST: incd x0, vl7
+// CHECK-ENCODING: [0xe0,0xe0,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e0 f0 04 <unknown>
+
+incd x0, vl8
+// CHECK-INST: incd x0, vl8
+// CHECK-ENCODING: [0x00,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e1 f0 04 <unknown>
+
+incd x0, vl16
+// CHECK-INST: incd x0, vl16
+// CHECK-ENCODING: [0x20,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e1 f0 04 <unknown>
+
+incd x0, vl32
+// CHECK-INST: incd x0, vl32
+// CHECK-ENCODING: [0x40,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e1 f0 04 <unknown>
+
+incd x0, vl64
+// CHECK-INST: incd x0, vl64
+// CHECK-ENCODING: [0x60,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e1 f0 04 <unknown>
+
+incd x0, vl128
+// CHECK-INST: incd x0, vl128
+// CHECK-ENCODING: [0x80,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e1 f0 04 <unknown>
+
+incd x0, vl256
+// CHECK-INST: incd x0, vl256
+// CHECK-ENCODING: [0xa0,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e1 f0 04 <unknown>
+
+incd x0, #14
+// CHECK-INST: incd x0, #14
+// CHECK-ENCODING: [0xc0,0xe1,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e1 f0 04 <unknown>
+
+incd x0, #28
+// CHECK-INST: incd x0, #28
+// CHECK-ENCODING: [0x80,0xe3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e3 f0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+inch w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: inch w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+inch sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: inch sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+inch x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: inch x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+inch x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: inch x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+inch x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: inch x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+inch x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: inch x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+inch x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: inch x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+inch x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: inch x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+inch x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: inch x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/inch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/inch.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/inch.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/inch.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+inch x0
+// CHECK-INST: inch x0
+// CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 70 04 <unknown>
+
+inch x0, all
+// CHECK-INST: inch x0
+// CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 70 04 <unknown>
+
+inch x0, all, mul #1
+// CHECK-INST: inch x0
+// CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 70 04 <unknown>
+
+inch x0, all, mul #16
+// CHECK-INST: inch x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe3,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 7f 04 <unknown>
+
+inch x0, pow2
+// CHECK-INST: inch x0, pow2
+// CHECK-ENCODING: [0x00,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 70 04 <unknown>
+
+inch x0, vl1
+// CHECK-INST: inch x0, vl1
+// CHECK-ENCODING: [0x20,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e0 70 04 <unknown>
+
+inch x0, vl2
+// CHECK-INST: inch x0, vl2
+// CHECK-ENCODING: [0x40,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e0 70 04 <unknown>
+
+inch x0, vl3
+// CHECK-INST: inch x0, vl3
+// CHECK-ENCODING: [0x60,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e0 70 04 <unknown>
+
+inch x0, vl4
+// CHECK-INST: inch x0, vl4
+// CHECK-ENCODING: [0x80,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e0 70 04 <unknown>
+
+inch x0, vl5
+// CHECK-INST: inch x0, vl5
+// CHECK-ENCODING: [0xa0,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e0 70 04 <unknown>
+
+inch x0, vl6
+// CHECK-INST: inch x0, vl6
+// CHECK-ENCODING: [0xc0,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e0 70 04 <unknown>
+
+inch x0, vl7
+// CHECK-INST: inch x0, vl7
+// CHECK-ENCODING: [0xe0,0xe0,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e0 70 04 <unknown>
+
+inch x0, vl8
+// CHECK-INST: inch x0, vl8
+// CHECK-ENCODING: [0x00,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e1 70 04 <unknown>
+
+inch x0, vl16
+// CHECK-INST: inch x0, vl16
+// CHECK-ENCODING: [0x20,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e1 70 04 <unknown>
+
+inch x0, vl32
+// CHECK-INST: inch x0, vl32
+// CHECK-ENCODING: [0x40,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e1 70 04 <unknown>
+
+inch x0, vl64
+// CHECK-INST: inch x0, vl64
+// CHECK-ENCODING: [0x60,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e1 70 04 <unknown>
+
+inch x0, vl128
+// CHECK-INST: inch x0, vl128
+// CHECK-ENCODING: [0x80,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e1 70 04 <unknown>
+
+inch x0, vl256
+// CHECK-INST: inch x0, vl256
+// CHECK-ENCODING: [0xa0,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e1 70 04 <unknown>
+
+inch x0, #14
+// CHECK-INST: inch x0, #14
+// CHECK-ENCODING: [0xc0,0xe1,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e1 70 04 <unknown>
+
+inch x0, #28
+// CHECK-INST: inch x0, #28
+// CHECK-ENCODING: [0x80,0xe3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e3 70 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid result register
+
+incw w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incw w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incw sp
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incw sp
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Immediate not compatible with encode/decode function.
+
+incw x0, all, mul #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incw x0, all, mul #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incw x0, all, mul #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incw x0, all, mul #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incw x0, all, mul #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: incw x0, all, mul #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate patterns
+
+incw x0, vl512
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incw x0, vl512
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incw x0, vl9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incw x0, vl9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incw x0, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incw x0, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incw x0, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: incw x0, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/incw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incw.s?rev=334838&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/incw.s Fri Jun 15 08:47:44 2018
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+incw x0
+// CHECK-INST: incw x0
+// CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 b0 04 <unknown>
+
+incw x0, all
+// CHECK-INST: incw x0
+// CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 b0 04 <unknown>
+
+incw x0, all, mul #1
+// CHECK-INST: incw x0
+// CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 b0 04 <unknown>
+
+incw x0, all, mul #16
+// CHECK-INST: incw x0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xe3,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e3 bf 04 <unknown>
+
+incw x0, pow2
+// CHECK-INST: incw x0, pow2
+// CHECK-ENCODING: [0x00,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 b0 04 <unknown>
+
+incw x0, vl1
+// CHECK-INST: incw x0, vl1
+// CHECK-ENCODING: [0x20,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e0 b0 04 <unknown>
+
+incw x0, vl2
+// CHECK-INST: incw x0, vl2
+// CHECK-ENCODING: [0x40,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e0 b0 04 <unknown>
+
+incw x0, vl3
+// CHECK-INST: incw x0, vl3
+// CHECK-ENCODING: [0x60,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e0 b0 04 <unknown>
+
+incw x0, vl4
+// CHECK-INST: incw x0, vl4
+// CHECK-ENCODING: [0x80,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e0 b0 04 <unknown>
+
+incw x0, vl5
+// CHECK-INST: incw x0, vl5
+// CHECK-ENCODING: [0xa0,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e0 b0 04 <unknown>
+
+incw x0, vl6
+// CHECK-INST: incw x0, vl6
+// CHECK-ENCODING: [0xc0,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e0 b0 04 <unknown>
+
+incw x0, vl7
+// CHECK-INST: incw x0, vl7
+// CHECK-ENCODING: [0xe0,0xe0,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 e0 b0 04 <unknown>
+
+incw x0, vl8
+// CHECK-INST: incw x0, vl8
+// CHECK-ENCODING: [0x00,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e1 b0 04 <unknown>
+
+incw x0, vl16
+// CHECK-INST: incw x0, vl16
+// CHECK-ENCODING: [0x20,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 e1 b0 04 <unknown>
+
+incw x0, vl32
+// CHECK-INST: incw x0, vl32
+// CHECK-ENCODING: [0x40,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 40 e1 b0 04 <unknown>
+
+incw x0, vl64
+// CHECK-INST: incw x0, vl64
+// CHECK-ENCODING: [0x60,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 60 e1 b0 04 <unknown>
+
+incw x0, vl128
+// CHECK-INST: incw x0, vl128
+// CHECK-ENCODING: [0x80,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e1 b0 04 <unknown>
+
+incw x0, vl256
+// CHECK-INST: incw x0, vl256
+// CHECK-ENCODING: [0xa0,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 e1 b0 04 <unknown>
+
+incw x0, #14
+// CHECK-INST: incw x0, #14
+// CHECK-ENCODING: [0xc0,0xe1,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c0 e1 b0 04 <unknown>
+
+incw x0, #28
+// CHECK-INST: incw x0, #28
+// CHECK-ENCODING: [0x80,0xe3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 80 e3 b0 04 <unknown>
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