[PATCH] D46365: AMDGPU: Separate R600 and GCN TableGen files

[Jan Vesely via Phabricator via llvm-commits]

jvesely added a comment.

I assume that there is no change in generated code intended for r600 (EG/CM).
These are the changes in piglit tests I noticed:

  < 	MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
  ---
  > 	MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X

There are other changes wrt register allocation and packetizer, but this one looks the most suspicious. My turks is TS2 and STORE_DWORD is not defined in the ISA (STORE_RAW is the only allowed opcode for CACHELESS target). Checking cayman ISA STORE_DWORD is opcode 20 (vs. opc 2 for STORE_RAW), which is reserved on TS2. The instruction also lost the offset.

Now, there are tests for MEMRAT_CACHELESS stoers, and they pass so I guess there is another untested store path that got mixed between TS2 and TS3.
I can paste the  .ll file if you're interested.


Repository:
  rL LLVM

https://reviews.llvm.org/D46365