[llvm] r334757 - AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 14 12:26:37 PDT 2018
Author: tstellar
Date: Thu Jun 14 12:26:37 2018
New Revision: 334757
URL: http://llvm.org/viewvc/llvm-project?rev=334757&view=rev
Log:
AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45907
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td?rev=334757&r1=334756&r2=334757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td Thu Jun 14 12:26:37 2018
@@ -46,5 +46,38 @@ class GISelVop2Pat <
(inst src0_vt:$src0, src1_vt:$src1)
>;
+class GISelVop2CommutePat <
+ SDPatternOperator node,
+ Instruction inst,
+ ValueType dst_vt,
+ ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
+
+ (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
+ (inst src0_vt:$src0, src1_vt:$src1)
+>;
+
+multiclass GISelVop2IntrPat <
+ SDPatternOperator node, Instruction inst,
+ ValueType dst_vt, ValueType src_vt = dst_vt> {
+
+ def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
+
+ // FIXME: Intrinsics aren't marked as commutable, so we need to add an explcit
+ // pattern to handle commuting. This is another reason why legalizing to a
+ // generic machine instruction may be better that matching the intrinsic
+ // directly.
+ def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
+}
+
def : GISelSop2Pat <or, S_OR_B32, i32>;
def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
+
+// FIXME: Select directly to _e32 so we don't need to deal with modifiers.
+// FIXME: We can't re-use SelectionDAG patterns here because they match
+// against a custom SDNode and we would need to create a generic machine
+// instruction that is equivalent to the custom SDNode. This would also require
+// us to custom legalize the intrinsic to the new generic machine instruction,
+// but I can't get custom legalizing of intrinsic to work and I'm not sure if
+// this is even supported yet.
+defm : GISelVop2IntrPat <
+ int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=334757&r1=334756&r2=334757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Thu Jun 14 12:26:37 2018
@@ -159,6 +159,19 @@ bool AMDGPUInstructionSelector::selectG_
return selectG_ADD(I);
}
+bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
+ CodeGenCoverage &CoverageInfo) const {
+ unsigned IntrinsicID = I.getOperand(1).getIntrinsicID();
+
+ switch (IntrinsicID) {
+ default:
+ break;
+ case Intrinsic::amdgcn_cvt_pkrtz:
+ return selectImpl(I, CoverageInfo);
+ }
+ return false;
+}
+
bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
@@ -522,6 +535,8 @@ bool AMDGPUInstructionSelector::select(M
return selectG_CONSTANT(I);
case TargetOpcode::G_GEP:
return selectG_GEP(I);
+ case TargetOpcode::G_INTRINSIC:
+ return selectG_INTRINSIC(I, CoverageInfo);
case TargetOpcode::G_LOAD:
return selectG_LOAD(I);
case TargetOpcode::G_STORE:
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h?rev=334757&r1=334756&r2=334757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h Thu Jun 14 12:26:37 2018
@@ -63,6 +63,7 @@ private:
bool selectG_CONSTANT(MachineInstr &I) const;
bool selectG_ADD(MachineInstr &I) const;
bool selectG_GEP(MachineInstr &I) const;
+ bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
SmallVectorImpl<GEPInfo> &AddrInfo) const;
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir?rev=334757&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir Thu Jun 14 12:26:37 2018
@@ -0,0 +1,44 @@
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+ define void @cvt_pkrtz(i32 addrspace(1)* %global0) { ret void }
+...
+---
+
+name: cvt_pkrtz
+legalized: true
+regBankSelected: true
+
+# GCN-LABEL: name: cvt_pkrtz
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
+
+ ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ %0:sgpr(s32) = COPY $sgpr0
+ ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ ; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr1
+ %3:vgpr(s64) = COPY $vgpr3_vgpr4
+
+ ; cvt_pkrtz vs
+ ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[SGPR0]], [[VGPR0]]
+ %4:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %0
+
+ ; cvt_pkrtz sv
+ ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[SGPR0]], [[VGPR0]]
+ %5:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
+
+ ; cvt_pkrtz vv
+ ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[VGPR0]], [[VGPR1]]
+ %6:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %2
+
+ %7:vgpr(s32) = G_BITCAST %4
+ %8:vgpr(s32) = G_BITCAST %5
+ %9:vgpr(s32) = G_BITCAST %6
+ G_STORE %7, %3 :: (store 4 into %ir.global0)
+ G_STORE %8, %3 :: (store 4 into %ir.global0)
+ G_STORE %9, %3 :: (store 4 into %ir.global0)
+...
+---
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