[llvm] r334744 - [x86] add tests for AVX1 FP logic op abuse (PR37749); NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 14 11:08:06 PDT 2018
Author: spatel
Date: Thu Jun 14 11:08:06 2018
New Revision: 334744
URL: http://llvm.org/viewvc/llvm-project?rev=334744&view=rev
Log:
[x86] add tests for AVX1 FP logic op abuse (PR37749); NFC
Also, add a RUN for AVX2 to make sure that's good.
Modified:
llvm/trunk/test/CodeGen/X86/avx-logic.ll
Modified: llvm/trunk/test/CodeGen/X86/avx-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-logic.ll?rev=334744&r1=334743&r2=334744&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-logic.ll Thu Jun 14 11:08:06 2018
@@ -1,14 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=ANY,AVX1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=ANY,INT256,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefixes=ANY,INT256,AVX512
define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: andpd256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandpd %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andpd256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandpd %ymm0, %ymm1, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %x to <4 x i64>
%1 = bitcast <4 x double> %y to <4 x i64>
@@ -20,12 +21,12 @@ entry:
}
define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
-; CHECK-LABEL: andpd256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andpd256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %y to <4 x i64>
%and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
@@ -36,10 +37,10 @@ entry:
}
define <8 x float> @andps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: andps256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandps %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andps256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandps %ymm0, %ymm1, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %x to <8 x i32>
%1 = bitcast <8 x float> %y to <8 x i32>
@@ -49,10 +50,10 @@ entry:
}
define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
-; CHECK-LABEL: andps256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andps256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %y to <8 x i32>
%and.i = and <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938>
@@ -61,12 +62,12 @@ entry:
}
define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: xorpd256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorpd %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: xorpd256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vxorpd %ymm0, %ymm1, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %x to <4 x i64>
%1 = bitcast <4 x double> %y to <4 x i64>
@@ -78,12 +79,12 @@ entry:
}
define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
-; CHECK-LABEL: xorpd256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: xorpd256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %y to <4 x i64>
%xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
@@ -94,10 +95,10 @@ entry:
}
define <8 x float> @xorps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: xorps256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorps %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: xorps256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vxorps %ymm0, %ymm1, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %x to <8 x i32>
%1 = bitcast <8 x float> %y to <8 x i32>
@@ -107,10 +108,10 @@ entry:
}
define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
-; CHECK-LABEL: xorps256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: xorps256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %y to <8 x i32>
%xor.i = xor <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938>
@@ -119,12 +120,12 @@ entry:
}
define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: orpd256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vorpd %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: orpd256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vorpd %ymm0, %ymm1, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %x to <4 x i64>
%1 = bitcast <4 x double> %y to <4 x i64>
@@ -136,12 +137,12 @@ entry:
}
define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
-; CHECK-LABEL: orpd256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: orpd256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %y to <4 x i64>
%or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
@@ -152,10 +153,10 @@ entry:
}
define <8 x float> @orps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: orps256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vorps %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: orps256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vorps %ymm0, %ymm1, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %x to <8 x i32>
%1 = bitcast <8 x float> %y to <8 x i32>
@@ -165,10 +166,10 @@ entry:
}
define <8 x float> @orps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
-; CHECK-LABEL: orps256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: orps256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %y to <8 x i32>
%or.i = or <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938>
@@ -177,12 +178,12 @@ entry:
}
define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: andnotpd256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandnpd %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andnotpd256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandnpd %ymm0, %ymm1, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <4 x double> %x to <4 x i64>
%neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
@@ -195,12 +196,12 @@ entry:
}
define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp {
-; CHECK-LABEL: andnotpd256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandnpd (%rdi), %ymm0, %ymm0
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andnotpd256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandnpd (%rdi), %ymm0, %ymm0
+; ANY-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vaddpd %ymm1, %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%tmp2 = load <4 x double>, <4 x double>* %x, align 32
%0 = bitcast <4 x double> %y to <4 x i64>
@@ -214,10 +215,10 @@ entry:
}
define <8 x float> @andnotps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
-; CHECK-LABEL: andnotps256:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandnps %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andnotps256:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandnps %ymm0, %ymm1, %ymm0
+; ANY-NEXT: retq
entry:
%0 = bitcast <8 x float> %x to <8 x i32>
%neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
@@ -228,10 +229,10 @@ entry:
}
define <8 x float> @andnotps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp {
-; CHECK-LABEL: andnotps256fold:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vandnps (%rdi), %ymm0, %ymm0
-; CHECK-NEXT: retq
+; ANY-LABEL: andnotps256fold:
+; ANY: # %bb.0: # %entry
+; ANY-NEXT: vandnps (%rdi), %ymm0, %ymm0
+; ANY-NEXT: retq
entry:
%tmp2 = load <8 x float>, <8 x float>* %x, align 32
%0 = bitcast <8 x float> %y to <8 x i32>
@@ -245,14 +246,13 @@ entry:
;;; Test that basic 2 x i64 logic use the integer version on AVX
define <2 x i64> @vpandn(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
-; CHECK-LABEL: vpandn:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vpsubq %xmm1, %xmm0, %xmm1
-; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: retq
-entry:
; Force the execution domain with an add.
+; ANY-LABEL: vpandn:
+; ANY: # %bb.0:
+; ANY-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; ANY-NEXT: vpsubq %xmm1, %xmm0, %xmm1
+; ANY-NEXT: vpandn %xmm0, %xmm1, %xmm0
+; ANY-NEXT: retq
%a2 = add <2 x i64> %a, <i64 1, i64 1>
%y = xor <2 x i64> %a2, <i64 -1, i64 -1>
%x = and <2 x i64> %a, %y
@@ -260,48 +260,223 @@ entry:
}
define <2 x i64> @vpand(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
-; CHECK-LABEL: vpand:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT: vpsubq %xmm2, %xmm0, %xmm0
-; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: retq
-entry:
; Force the execution domain with an add.
+; ANY-LABEL: vpand:
+; ANY: # %bb.0:
+; ANY-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; ANY-NEXT: vpsubq %xmm2, %xmm0, %xmm0
+; ANY-NEXT: vpand %xmm1, %xmm0, %xmm0
+; ANY-NEXT: retq
%a2 = add <2 x i64> %a, <i64 1, i64 1>
%x = and <2 x i64> %a2, %b
ret <2 x i64> %x
}
define <4 x i32> @and_xor_splat1_v4i32(<4 x i32> %x) nounwind {
-; AVX-LABEL: and_xor_splat1_v4i32:
-; AVX: # %bb.0:
-; AVX-NEXT: vandnps {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: and_xor_splat1_v4i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vandnps {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: retq
;
-; AVX512-LABEL: and_xor_splat1_v4i32:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
-; AVX512-NEXT: vandnps %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: retq
+; INT256-LABEL: and_xor_splat1_v4i32:
+; INT256: # %bb.0:
+; INT256-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
+; INT256-NEXT: vandnps %xmm1, %xmm0, %xmm0
+; INT256-NEXT: retq
%xor = xor <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
%and = and <4 x i32> %xor, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %and
}
define <4 x i64> @and_xor_splat1_v4i64(<4 x i64> %x) nounwind {
-; AVX-LABEL: and_xor_splat1_v4i64:
-; AVX: # %bb.0:
-; AVX-NEXT: vandnps {{.*}}(%rip), %ymm0, %ymm0
-; AVX-NEXT: retq
+; AVX1-LABEL: and_xor_splat1_v4i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vandnps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: retq
;
-; AVX512-LABEL: and_xor_splat1_v4i64:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vbroadcastsd {{.*#+}} ymm1 = [1,1,1,1]
-; AVX512-NEXT: vandnps %ymm1, %ymm0, %ymm0
-; AVX512-NEXT: retq
+; INT256-LABEL: and_xor_splat1_v4i64:
+; INT256: # %bb.0:
+; INT256-NEXT: vbroadcastsd {{.*#+}} ymm1 = [1,1,1,1]
+; INT256-NEXT: vandnps %ymm1, %ymm0, %ymm0
+; INT256-NEXT: retq
%xor = xor <4 x i64> %x, <i64 1, i64 1, i64 1, i64 1>
%and = and <4 x i64> %xor, <i64 1, i64 1, i64 1, i64 1>
ret <4 x i64> %and
}
+; PR37749 - https://bugs.llvm.org/show_bug.cgi?id=37749
+; For AVX1, we don't want a 256-bit logic op with insert/extract to the surrounding 128-bit ops.
+
+define <8 x i32> @and_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: and_disguised_i8_elts:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vpaddd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
+; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; INT256-LABEL: and_disguised_i8_elts:
+; INT256: # %bb.0:
+; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT: retq
+ %a = add <8 x i32> %x, %y
+ %l = and <8 x i32> %a, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
+ %t = add <8 x i32> %l, %z
+ ret <8 x i32> %t
+}
+
+define <8 x i32> @or_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: or_disguised_i8_elts:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1095216660735,1095216660735]
+; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; AVX1-NEXT: vpor %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; INT256-LABEL: or_disguised_i8_elts:
+; INT256: # %bb.0:
+; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpbroadcastd {{.*#+}} ymm1 = [255,255,255,255,255,255,255,255]
+; INT256-NEXT: vpor %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT: retq
+ %a = add <8 x i32> %x, %y
+ %l = or <8 x i32> %a, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
+ %t = add <8 x i32> %l, %z
+ ret <8 x i32> %t
+}
+
+define <8 x i32> @xor_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: xor_disguised_i8_elts:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1095216660735,1095216660735]
+; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; AVX1-NEXT: vpxor %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; INT256-LABEL: xor_disguised_i8_elts:
+; INT256: # %bb.0:
+; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpbroadcastd {{.*#+}} ymm1 = [255,255,255,255,255,255,255,255]
+; INT256-NEXT: vpxor %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT: retq
+ %a = add <8 x i32> %x, %y
+ %l = xor <8 x i32> %a, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
+ %t = add <8 x i32> %l, %z
+ ret <8 x i32> %t
+}
+
+define <8 x i32> @and_disguised_i16_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: and_disguised_i16_elts:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vpaddd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
+; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; INT256-LABEL: and_disguised_i16_elts:
+; INT256: # %bb.0:
+; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; INT256-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
+; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT: retq
+ %a = add <8 x i32> %x, %y
+ %l = and <8 x i32> %a, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
+ %t = add <8 x i32> %l, %z
+ ret <8 x i32> %t
+}
+
+define <8 x i32> @or_disguised_i16_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: or_disguised_i16_elts:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [281470681808895,281470681808895]
+; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; AVX1-NEXT: vpor %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; INT256-LABEL: or_disguised_i16_elts:
+; INT256: # %bb.0:
+; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpbroadcastd {{.*#+}} ymm1 = [65535,65535,65535,65535,65535,65535,65535,65535]
+; INT256-NEXT: vpor %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT: retq
+ %a = add <8 x i32> %x, %y
+ %l = or <8 x i32> %a, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
+ %t = add <8 x i32> %l, %z
+ ret <8 x i32> %t
+}
+
+define <8 x i32> @xor_disguised_i16_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: xor_disguised_i16_elts:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [281470681808895,281470681808895]
+; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; AVX1-NEXT: vpxor %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; INT256-LABEL: xor_disguised_i16_elts:
+; INT256: # %bb.0:
+; INT256-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpbroadcastd {{.*#+}} ymm1 = [65535,65535,65535,65535,65535,65535,65535,65535]
+; INT256-NEXT: vpxor %ymm1, %ymm0, %ymm0
+; INT256-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT: retq
+ %a = add <8 x i32> %x, %y
+ %l = xor <8 x i32> %a, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
+ %t = add <8 x i32> %l, %z
+ ret <8 x i32> %t
+}
+
More information about the llvm-commits
mailing list