[PATCH] D48168: AMDGPU: Remove redundant MIMG instruction variants

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle created this revision.
nhaehnle added reviewers: arsenm, rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, wdng, kzhuravl.

For sample and gather ops, we can accurately determine the set of
vaddr-size instruction variants that are required. This reduces
the size of instruction tables by ~5%.

The number of machine instruction opcodes is reduced from 10002
to 9476.

Change-Id: Ie7fc65d3657b762c7816017fe70b2e9bec644a8a


Repository:
  rL LLVM

https://reviews.llvm.org/D48168

Files:
  lib/Target/AMDGPU/MIMGInstructions.td
  test/MC/AMDGPU/gfx7_asm_all.s
  test/MC/AMDGPU/gfx8_asm_all.s

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