[llvm] r334708 - [mips] Correct predicates for MSA pseudo instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 14 06:03:53 PDT 2018
Author: sdardis
Date: Thu Jun 14 06:03:53 2018
New Revision: 334708
URL: http://llvm.org/viewvc/llvm-project?rev=334708&view=rev
Log:
[mips] Correct predicates for MSA pseudo instructions
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=334708&r1=334707&r2=334708&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Thu Jun 14 06:03:53 2018
@@ -24,7 +24,8 @@ class MSASpecial : MSAInst {
class MSAPseudo<dag outs, dag ins, list<dag> pattern,
InstrItinClass itin = IIPseudo>:
MipsPseudo<outs, ins, pattern, itin> {
- let Predicates = [HasMSA];
+ let EncodingPredicates = [HasStdEnc];
+ let ASEPredicate = [HasMSA];
}
class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
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