[llvm] r334622 - [AMDGPU][MC] Enabled parsing of relocations on VALU instructions

[Dmitry Preobrazhensky via llvm-commits]

Author: dpreobra
Date: Wed Jun 13 10:02:03 2018
New Revision: 334622

URL: http://llvm.org/viewvc/llvm-project?rev=334622&view=rev
Log:
[AMDGPU][MC] Enabled parsing of relocations on VALU instructions

See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566

Reviewers: artem.tamazov, arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D47884

Modified:
    llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    llvm/trunk/test/MC/AMDGPU/expressions.s
    llvm/trunk/test/MC/AMDGPU/reloc.s

Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=334622&r1=334621&r2=334622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Wed Jun 13 10:02:03 2018
@@ -443,7 +443,7 @@ public:
   }
 
   bool isVSrcB32() const {
-    return isVCSrcF32() || isLiteralImm(MVT::i32);
+    return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr();
   }
 
   bool isVSrcB64() const {
@@ -460,7 +460,7 @@ public:
   }
 
   bool isVSrcF32() const {
-    return isVCSrcF32() || isLiteralImm(MVT::f32);
+    return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr();
   }
 
   bool isVSrcF64() const {

Modified: llvm/trunk/test/MC/AMDGPU/expressions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/expressions.s?rev=334622&r1=334621&r2=334622&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/expressions.s (original)
+++ llvm/trunk/test/MC/AMDGPU/expressions.s Wed Jun 13 10:02:03 2018
@@ -40,6 +40,9 @@ s_mov_b32 s0, foo+2
 s_mov_b32 s0, foo+2
 // VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]
 
+v_mul_f32 v0, foo+2, v2
+// VI: v_mul_f32_e32 v0, 514, v2 ; encoding: [0xff,0x04,0x00,0x0a,0x02,0x02,0x00,0x00]
+
 BB1:
 v_nop_e64
 BB2:

Modified: llvm/trunk/test/MC/AMDGPU/reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/reloc.s?rev=334622&r1=334621&r2=334622&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/reloc.s (original)
+++ llvm/trunk/test/MC/AMDGPU/reloc.s Wed Jun 13 10:02:03 2018
@@ -9,6 +9,13 @@
 // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
 // CHECK: R_AMDGPU_REL32_LO global_var3 0x0
 // CHECK: R_AMDGPU_REL32_HI global_var4 0x0
+// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
+// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
+// CHECK: R_AMDGPU_GOTPCREL global_var0 0x0
+// CHECK: R_AMDGPU_GOTPCREL32_LO global_var1 0x0
+// CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
+// CHECK: R_AMDGPU_REL32_LO global_var3 0x0
+// CHECK: R_AMDGPU_REL32_HI global_var4 0x0
 // CHECK: R_AMDGPU_ABS32 var 0x0
 // CHECK: }
 // CHECK: .rel.data {
@@ -26,6 +33,14 @@ kernel:
   s_mov_b32 s5, global_var3 at rel32@lo
   s_mov_b32 s6, global_var4 at rel32@hi
 
+  v_mov_b32 v0, SCRATCH_RSRC_DWORD0
+  v_mov_b32 v1, SCRATCH_RSRC_DWORD1
+  v_mov_b32 v2, global_var0 at GOTPCREL
+  v_mov_b32 v3, global_var1 at gotpcrel32@lo
+  v_mov_b32 v4, global_var2 at gotpcrel32@hi
+  v_mov_b32 v5, global_var3 at rel32@lo
+  v_mov_b32 v6, global_var4 at rel32@hi
+
 .globl global_var0
 .globl global_var1
 .globl global_var2