[llvm] r334605 - [x86] add test for fadd with more than one use; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Wed Jun 13 08:01:07 2018
New Revision: 334605

URL: http://llvm.org/viewvc/llvm-project?rev=334605&view=rev
Log:
[x86] add test for fadd with more than one use; NFC

The equivalent AArch64 test added at rL334556 isn't showing
the expected output from the DAGCombiner code change that 
would fix this example. That's a machine combiner bug from 
what I see.

Modified:
    llvm/trunk/test/CodeGen/X86/fadd-combines.ll

Modified: llvm/trunk/test/CodeGen/X86/fadd-combines.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fadd-combines.ll?rev=334605&r1=334604&r2=334605&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fadd-combines.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fadd-combines.ll Wed Jun 13 08:01:07 2018
@@ -221,4 +221,23 @@ define <4 x float> @fadd_fadd_x_x_fadd_x
   ret <4 x float> %z
 }
 
+; FIXME:
+; ((x + 42.0) + 17.0) + (x + 42.0) --> (x + 59.0) + (x + 17.0)
+; It's still 3 adds, but the first two are independent.
+; More reassocation could get this to 2 adds or 1 FMA (that's done in IR, but not in the DAG).
+
+define float @fadd_const_multiuse_attr(float %x) #0 {
+; CHECK-LABEL: fadd_const_multiuse_attr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addss {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT:    addss %xmm0, %xmm1
+; CHECK-NEXT:    addss %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %a1 = fadd float %x, 42.0
+  %a2 = fadd float %a1, 17.0
+  %a3 = fadd float %a1, %a2
+  ret float %a3
+}
+
 attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "no-signed-zeros-fp-math"="true" }