sdardis added inline comments.
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Comment at: lib/Target/Mips/MipsBranchExpansion.cpp:364
+unsigned MipsBranchExpansion::getJROp() {
+ if (ABI.IsN64())
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Sorry, better idea here.
Instead, turn this into a wrapper around BuildMI, taking the first 3 arguments of BuildMI.
Compute the relevant opcode for all possible variants including microMIPS, Call out to BuildMI with the computed opcode adding the right AT/AT_64 register, then conditionally add the immediate of zero for R6 if required.
Then return true/false if the inserted instruction has a delay slot.
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Comment at: lib/Target/Mips/MipsBranchExpansion.cpp:495-518
if (STI->isTargetNaCl() ||
(STI->hasMips32r6() && !STI->useIndirectJumpsHazard()))
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP)
.addImm(8);
if (STI->hasMips32r6() && !STI->useIndirectJumpsHazard()) {
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This can all be refactored then. Insert the branch instruction with the extended helper. If the inserted instruction has no delay slot or the target is NaCl, put the stack adjustment before the inserted instruction. Otherwise insert the nop/stack adjust as appropriate after the jump and bundle it with the branch.
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Comment at: lib/Target/Mips/MipsBranchExpansion.cpp:609-621
if (STI->hasMips64r6() && !STI->useIndirectJumpsHazard()) {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
.addReg(Mips::SP_64)
.addImm(16);
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JIC64))
.addReg(Mips::AT_64)
.addImm(0);
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Similarly here. This code is missing the NaCl changes.
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Comment at: lib/Target/Mips/MipsBranchExpansion.cpp:688-707
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(getJROp())).addReg(Mips::AT_64);
+ } else {
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi))
+ .addReg(Mips::AT)
+ .addMBB(TgtMBB, MipsII::MO_ABS_HI);
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_ADDiu),
+ Mips::AT)
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The tail of the N64 case and the tail of the N32/O32 case where the jump instruction is inserted here can be merged here with the extended helper, conditionally bundling the NOP if required.
https://reviews.llvm.org/D48019