[PATCH] D48123: [llvm-exegesis] Fix failing assert when creating Snippet for LAHF.

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet created this revision.
gchatelet added a reviewer: courbet.
Herald added subscribers: llvm-commits, tschuett.

Repository:
  rL LLVM

https://reviews.llvm.org/D48123

Files:
  tools/llvm-exegesis/lib/MCInstrDescView.cpp
  unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp


Index: unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
===================================================================
--- unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -103,11 +103,22 @@
 
   const unsigned Opcode = llvm::X86::CMP64rr;
   auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through CMOVLE16rr"));
+  EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through"));
   ASSERT_THAT(Conf.Snippet, testing::SizeIs(2));
+  const llvm::MCInst Instr = Conf.Snippet[0];
+  EXPECT_THAT(Instr.getOpcode(), Opcode);
   // TODO: check that the two instructions alias each other.
 }
 
+TEST_F(LatencySnippetGeneratorTest, LAHF) {
+  const unsigned Opcode = llvm::X86::LAHF;
+  auto Conf = checkAndGetConfiguration(Opcode);
+  EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through"));
+  ASSERT_THAT(Conf.Snippet, testing::SizeIs(2));
+  const llvm::MCInst Instr = Conf.Snippet[0];
+  EXPECT_THAT(Instr.getOpcode(), Opcode);
+}
+
 class UopsSnippetGeneratorTest : public X86SnippetGeneratorTest {
 protected:
   UopsSnippetGeneratorTest() : Runner(State) {}
Index: tools/llvm-exegesis/lib/MCInstrDescView.cpp
===================================================================
--- tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -208,13 +208,17 @@
 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
                                     InstructionInstance &II) {
   assert(ROV.Op);
-  assert(ROV.Op->IsExplicit);
-  auto &AssignedValue = II.getValueFor(*ROV.Op);
-  if (AssignedValue.isValid()) {
-    assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
-    return;
+  if (ROV.Op->IsExplicit) {
+    auto &AssignedValue = II.getValueFor(*ROV.Op);
+    if (AssignedValue.isValid()) {
+      assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
+      return;
+    }
+    AssignedValue = llvm::MCOperand::createReg(ROV.Reg);
+  } else {
+    assert(ROV.Op->ImplicitReg != nullptr);
+    assert(ROV.Reg == *ROV.Op->ImplicitReg);
   }
-  AssignedValue = llvm::MCOperand::createReg(ROV.Reg);
 }
 
 size_t randomBit(const llvm::BitVector &Vector) {


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