[llvm] r334586 - [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
Clement Courbet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 13 02:41:49 PDT 2018
Author: courbet
Date: Wed Jun 13 02:41:49 2018
New Revision: 334586
URL: http://llvm.org/viewvc/llvm-project?rev=334586&view=rev
Log:
[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
Summary:
For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files.
For more obvious cases, I've ventured a fix.
Some notes:
- Exynos is especially fishy.
- AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice.
- The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit.
Also see PR37310.
Reviewers: RKSimon, craig.topper, javed.absar
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46356
Modified:
llvm/trunk/include/llvm/Target/TargetSchedule.td
llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td?rev=334586&r1=334585&r2=334586&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSchedule.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSchedule.td Wed Jun 13 02:41:49 2018
@@ -281,10 +281,9 @@ class ProcWriteResources<list<ProcResour
// ProcResources indicates the set of resources consumed by the write.
// Optionally, ResourceCycles indicates the number of cycles the
// resource is consumed. Each ResourceCycles item is paired with the
-// ProcResource item at the same position in its list. Since
-// ResourceCycles are rarely specialized, the list may be
-// incomplete. By default, resources are consumed for a single cycle,
-// regardless of latency, which models a fully pipelined processing
+// ProcResource item at the same position in its list. ResourceCycles
+// can be `[]`: in that case, all resources are consumed for a single
+// cycle, regardless of latency, which models a fully pipelined processing
// unit. A value of 0 for ResourceCycles means that the resource must
// be available but is not consumed, which is only relevant for
// unbuffered resources.
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td?rev=334586&r1=334585&r2=334586&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td Wed Jun 13 02:41:49 2018
@@ -416,7 +416,7 @@ def : InstRW<[THX2T99Write_1Cyc_I2],
// Address generation
def : WriteRes<WriteI, [THX2T99I012]> {
let Latency = 1;
- let ResourceCycles = [1, 3];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -438,7 +438,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX2T99I012]> {
let Latency = 2;
- let ResourceCycles = [2, 3];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
@@ -457,7 +457,7 @@ def : InstRW<[WriteISReg],
def : WriteRes<WriteIEReg, [THX2T99I012]> {
let Latency = 1;
- let ResourceCycles = [1, 3];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -500,14 +500,14 @@ def : WriteRes<WriteIS, [THX2T99I01
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX2T99I1]> {
let Latency = 39;
- let ResourceCycles = [13, 39];
+ let ResourceCycles = [39];
let NumMicroOps = 4;
}
// Divide, X-form
def : WriteRes<WriteID64, [THX2T99I1]> {
let Latency = 23;
- let ResourceCycles = [13, 23];
+ let ResourceCycles = [23];
let NumMicroOps = 4;
}
@@ -1252,7 +1252,7 @@ def : InstRW<[THX2T99Write_5Cyc_F01], (i
def : WriteRes<WriteV, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
- let ResourceCycles = [4, 23];
+ let ResourceCycles = [4];
}
// ASIMD arith, reduce, 4H/4S
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=334586&r1=334585&r2=334586&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Wed Jun 13 02:41:49 2018
@@ -941,8 +941,7 @@ Record *SubtargetEmitter::FindReadAdvanc
void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
std::vector<int64_t> &Cycles,
const CodeGenProcModel &PM) {
- // Default to 1 resource cycle.
- Cycles.resize(PRVec.size(), 1);
+ assert(PRVec.size() == Cycles.size() && "failed precondition");
for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
Record *PRDef = PRVec[i];
RecVec SubResources;
@@ -1111,6 +1110,21 @@ void SubtargetEmitter::GenSchedClassTabl
std::vector<int64_t> Cycles =
WriteRes->getValueAsListOfInts("ResourceCycles");
+ if (Cycles.empty()) {
+ // If ResourceCycles is not provided, default to one cycle per
+ // resource.
+ Cycles.resize(PRVec.size(), 1);
+ } else if (Cycles.size() != PRVec.size()) {
+ // If ResourceCycles is provided, check consistency.
+ PrintFatalError(
+ WriteRes->getLoc(),
+ Twine("Inconsistent resource cycles: !size(ResourceCycles) != "
+ "!size(ProcResources): ")
+ .concat(Twine(PRVec.size()))
+ .concat(" vs ")
+ .concat(Twine(Cycles.size())));
+ }
+
ExpandProcResources(PRVec, Cycles, ProcModel);
for (unsigned PRIdx = 0, PREnd = PRVec.size();
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