[llvm] r334583 - [PowerPC] fix trivial typos in comment, NFC
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 13 01:54:14 PDT 2018
Author: inouehrs
Date: Wed Jun 13 01:54:13 2018
New Revision: 334583
URL: http://llvm.org/viewvc/llvm-project?rev=334583&view=rev
Log:
[PowerPC] fix trivial typos in comment, NFC
Modified:
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
llvm/trunk/lib/Target/PowerPC/PPCExpandISEL.cpp
llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Jun 13 01:54:13 2018
@@ -1283,7 +1283,7 @@ void PPCLinuxAsmPrinter::EmitFunctionEnt
if (Subtarget->isELFv2ABI()) {
// In the Large code model, we allow arbitrary displacements between
// the text section and its associated TOC section. We place the
- // full 8-byte offset to the TOC in memory immediatedly preceding
+ // full 8-byte offset to the TOC in memory immediately preceding
// the function global entry point.
if (TM.getCodeModel() == CodeModel::Large
&& !MF->getRegInfo().use_empty(PPC::X2)) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp Wed Jun 13 01:54:13 2018
@@ -588,7 +588,7 @@ bool PPCCTRLoops::convertToCTRLoop(Loop
// We now have a loop-invariant count of loop iterations (which is not the
// constant zero) for which we know that this loop will not exit via this
- // exisiting block.
+ // existing block.
// We need to make sure that this block will run on every loop iteration.
// For this to be true, we must dominate all blocks with backedges. Such
Modified: llvm/trunk/lib/Target/PowerPC/PPCExpandISEL.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCExpandISEL.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCExpandISEL.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCExpandISEL.cpp Wed Jun 13 01:54:13 2018
@@ -117,7 +117,7 @@ public:
/// instruction is still generated by default on targets that support them.
///
/// \return true if ISEL should be expanded into if-then-else code sequence;
- /// false if ISEL instruction should be generated, i.e. not expaned.
+ /// false if ISEL instruction should be generated, i.e. not expanded.
///
static bool isExpandISELEnabled(const MachineFunction &MF);
@@ -212,7 +212,7 @@ void PPCExpandISEL::expandAndMergeISELs(
// as it would be ISEL %R0, %ZERO, %R0, %CRN.
if (useSameRegister(Dest, TrueValue) &&
useSameRegister(Dest, FalseValue)) {
- LLVM_DEBUG(dbgs() << "Remove redudant ISEL instruction: " << **I
+ LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction: " << **I
<< "\n");
// FIXME: if the CR field used has no other uses, we could eliminate the
// instruction that defines it. This would have to be done manually
@@ -227,7 +227,7 @@ void PPCExpandISEL::expandAndMergeISELs(
// safe to fold ISEL to MR(OR) instead of ADDI.
MachineBasicBlock *MBB = (*I)->getParent();
LLVM_DEBUG(
- dbgs() << "Fold the ISEL instruction to an unconditonal copy:\n");
+ dbgs() << "Fold the ISEL instruction to an unconditional copy:\n");
LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
NumFolded++;
// Note: we're using both the TrueValue and FalseValue operands so as
Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Wed Jun 13 01:54:13 2018
@@ -1615,7 +1615,7 @@ void PPCFrameLowering::determineCalleeSa
}
// Make sure we don't explicitly spill r31, because, for example, we have
- // some inline asm which explicity clobbers it, when we otherwise have a
+ // some inline asm which explicitly clobbers it, when we otherwise have a
// frame pointer and are using r31's spill slot for the prologue/epilogue
// code. Same goes for the base pointer and the PIC base register.
if (needsFP(MF))
@@ -1864,7 +1864,7 @@ void PPCFrameLowering::processFunctionBe
}
if (HasVRSaveArea) {
- // Insert alignment padding, we need 16-byte alignment. Note: for postive
+ // Insert alignment padding, we need 16-byte alignment. Note: for positive
// number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since
// we are using negative number here (the stack grows downward). We should
// use formula : y = x & (~(n-1)). Where x is the size before aligning, n
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jun 13 01:54:13 2018
@@ -309,7 +309,7 @@ PPCTargetLowering::PPCTargetLowering(con
// PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
// to speed up scalar BSWAP64.
- // CTPOP or CTTZ were introduced in P8/P9 respectivelly
+ // CTPOP or CTTZ were introduced in P8/P9 respectively
setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
if (Subtarget.isISA3_0()) {
setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
@@ -4293,7 +4293,7 @@ static int CalculateTailCallSPDiff(Selec
PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
unsigned CallerMinReservedArea = FI->getMinReservedArea();
int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
- // Remember only if the new adjustement is bigger.
+ // Remember only if the new adjustment is bigger.
if (SPDiff < FI->getTailCallSPDelta())
FI->setTailCallSPDelta(SPDiff);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Jun 13 01:54:13 2018
@@ -1608,7 +1608,7 @@ bool PPCInstrInfo::optimizeCompareInstr(
int OpC = CmpInstr.getOpcode();
unsigned CRReg = CmpInstr.getOperand(0).getReg();
- // FP record forms set CR1 based on the execption status bits, not a
+ // FP record forms set CR1 based on the exception status bits, not a
// comparison with zero.
if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
return false;
@@ -1731,7 +1731,7 @@ bool PPCInstrInfo::optimizeCompareInstr(
unsigned PredHint = PPC::getPredicateHint(Pred);
int16_t Immed = (int16_t)Value;
- // When modyfing the condition in the predicate, we propagate hint bits
+ // When modifying the condition in the predicate, we propagate hint bits
// from the original predicate to the new one.
if (Immed == -1 && PredCond == PPC::PRED_GT)
// We convert "greater than -1" into "greater than or equal to 0",
@@ -2233,7 +2233,7 @@ MachineInstr *PPCInstrInfo::getConstantD
MachineInstr *DefMI = nullptr;
MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
const TargetRegisterInfo *TRI = &getRegisterInfo();
- // If we'ere in SSA, get the defs through the MRI. Otherwise, only look
+ // If we're in SSA, get the defs through the MRI. Otherwise, only look
// within the basic block to see if the register is defined using an LI/LI8.
if (MRI->isSSA()) {
for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
@@ -3185,7 +3185,7 @@ bool PPCInstrInfo::isTOCSaveMI(const Mac
}
// We limit the max depth to track incoming values of PHIs or binary ops
-// (e.g. AND) to avoid exsessive cost.
+// (e.g. AND) to avoid excessive cost.
const unsigned MAX_DEPTH = 1;
bool
Modified: llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp Wed Jun 13 01:54:13 2018
@@ -190,18 +190,18 @@ getKnownLeadingZeroCount(MachineInstr *M
}
// This function maintains a map for the pairs <TOC Save Instr, Keep>
-// Each time a new TOC save is encountered, it checks if any of the exisiting
-// ones are dominated by the new one. If so, it marks the exisiting one as
+// Each time a new TOC save is encountered, it checks if any of the existing
+// ones are dominated by the new one. If so, it marks the existing one as
// redundant by setting it's entry in the map as false. It then adds the new
// instruction to the map with either true or false depending on if any
-// exisiting instructions dominated the new one.
+// existing instructions dominated the new one.
void PPCMIPeephole::UpdateTOCSaves(
std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) {
assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here");
bool Keep = true;
for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) {
MachineInstr *CurrInst = It->first;
- // If new instruction dominates an exisiting one, mark exisiting one as
+ // If new instruction dominates an existing one, mark existing one as
// redundant.
if (It->second && MDT->dominates(MI, CurrInst))
It->second = false;
@@ -276,7 +276,7 @@ bool PPCMIPeephole::simplifyCode(void) {
!MF->getSubtarget<PPCSubtarget>().isELFv2ABI())
break;
// When encountering a TOC save instruction, call UpdateTOCSaves
- // to add it to the TOCSaves map and mark any exisiting TOC saves
+ // to add it to the TOCSaves map and mark any existing TOC saves
// it dominates as redundant.
if (TII->isTOCSaveMI(MI))
UpdateTOCSaves(TOCSaves, &MI);
@@ -847,7 +847,7 @@ static unsigned getPredicateToIncImm(Mac
return 0;
}
-// This takes a Phi node and returns a register value for the spefied BB.
+// This takes a Phi node and returns a register value for the specified BB.
static unsigned getIncomingRegForBlock(MachineInstr *Phi,
MachineBasicBlock *MBB) {
for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) {
@@ -1190,7 +1190,7 @@ bool PPCMIPeephole::eliminateRedundantCo
}
}
- // We cannnot merge two compares if the immediates are not same.
+ // We cannot merge two compares if the immediates are not same.
if (NewImm2 != NewImm1)
continue;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Wed Jun 13 01:54:13 2018
@@ -196,11 +196,11 @@ public:
LiveInAttrs.push_back(std::make_pair(VReg, Flags));
}
- /// This function returns true if the spesified vreg is
+ /// This function returns true if the specified vreg is
/// a live-in register and sign-extended.
bool isLiveInSExt(unsigned VReg) const;
- /// This function returns true if the spesified vreg is
+ /// This function returns true if the specified vreg is
/// a live-in register and zero-extended.
bool isLiveInZExt(unsigned VReg) const;
Modified: llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp Wed Jun 13 01:54:13 2018
@@ -91,7 +91,7 @@ static void addIncomingValuesToPHIs(Mach
MachineBasicBlock *NewMBB,
MachineRegisterInfo *MRI) {
assert(OrigMBB->isSuccessor(NewMBB) &&
- "NewMBB must be a sucessor of OrigMBB");
+ "NewMBB must be a successor of OrigMBB");
for (auto &MI : Successor->instrs()) {
if (!MI.isPHI())
continue;
@@ -501,7 +501,7 @@ PPCReduceCRLogicals::createCRLogicalOpIn
return Ret;
}
-/// Looks trhough a COPY instruction to the actual definition of the CR-bit
+/// Looks through a COPY instruction to the actual definition of the CR-bit
/// register and returns the instruction that defines it.
/// FIXME: This currently handles what is by-far the most common case:
/// an instruction that defines a CR field followed by a single copy of a bit
@@ -699,7 +699,7 @@ void PPCReduceCRLogicals::collectCRLogic
}
}
-} // end annonymous namespace
+} // end anonymous namespace
INITIALIZE_PASS_BEGIN(PPCReduceCRLogicals, DEBUG_TYPE,
"PowerPC Reduce CR logical Operation", false, false)
Modified: llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp?rev=334583&r1=334582&r2=334583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp Wed Jun 13 01:54:13 2018
@@ -108,7 +108,7 @@ protected:
}
// We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
- // as schduling fence to avoid it is scheduled before
+ // as scheduling fence to avoid it is scheduled before
// mflr in the prologue and the address in LR is clobbered (PR25839).
// We don't really need to save data to the stack - the clobbered
// registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
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