[PATCH] D48078: [x86] eliminate even more sign-bit tests with vector select

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper.
Herald added a subscriber: mcrosier.

This shortcoming was noted in https://reviews.llvm.org/D47330, and the test diffs show we already had other examples where we failed to fold to a SHRUNKBLEND:

/// Dynamic (non-constant condition) vector blend where only the sign bits
/// of the condition elements are used. This is used to enforce that the
/// condition mask is not valid for generic VSELECT optimizations.

This patch implements an idea from https://reviews.llvm.org/D48043 and would obsolete that patch because it catches more cases (notable the AVX1 case that was missed there). All we're doing is allowing the existing transform to fire more often by removing the post-legalize constraint. All of the relevant feature checks and other predicates are left as-is.


https://reviews.llvm.org/D48078

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vsel-cmp-load.ll
  test/CodeGen/X86/vselect-pcmp.ll

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