[PATCH] D48043: [x86] eliminate more sign-bit tests with vector select

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: test/CodeGen/X86/vsel-cmp-load.ll:260
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
 ; AVX1-NEXT:    vblendvps %ymm2, %ymm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
----------------
spatel wrote:
> RKSimon wrote:
> > How come this folds but the AVX1 case in slt_zero above doesn't?
> AVX1 is more complicated due to ISA limitations, so I was planning to catch that one next. There, we've split the PCMPGT into halves, so I'll need to match a pattern with a concat:
> 
>         t41: v4i32 = X86ISD::PCMPGT t37, t32
>             t31: v8i16 = vector_shuffle<4,5,6,7,u,u,u,u> t28, undef:v8i16
>           t33: v4i32 = sign_extend_vector_inreg t31
>         t42: v4i32 = X86ISD::PCMPGT t37, t33
>       t40: v8i32 = concat_vectors t41, t42
>       t4: v8i32,ch = CopyFromReg t0, Register:v8i32 %1
>       t6: v8i32,ch = CopyFromReg t0, Register:v8i32 %2
>     t23: v8i32 = vselect t40, t4, t6
> 
Or probably easier - we match the pattern after type legalization, but before vector op legalization:
        t21: v8i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>
      t22: v8i32 = setcc t24, t21, setlt:ch
      t4: v8i32,ch = CopyFromReg t0, Register:v8i32 %1
      t6: v8i32,ch = CopyFromReg t0, Register:v8i32 %2
    t23: v8i32 = vselect t22, t4, t6



https://reviews.llvm.org/D48043