[PATCH] D48043: [x86] eliminate more sign-bit tests with vector select

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/X86/vsel-cmp-load.ll:252
 
 ; FIXME: The compare with 0 for AVX2 should be eliminated.
 
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This can go


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Comment at: test/CodeGen/X86/vsel-cmp-load.ll:260
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
 ; AVX1-NEXT:    vblendvps %ymm2, %ymm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
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How come this folds but the AVX1 case in slt_zero above doesn't?


https://reviews.llvm.org/D48043