[PATCH] D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:4505-4506
+
+      MVT StoreVT = VData.getSimpleValueType();
+      if (StoreVT == MVT::f16 || StoreVT == MVT::v2f16 || StoreVT == MVT::v4f16) {
+        if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS ||
----------------
.ScalarType() == s16


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:4507
+      if (StoreVT == MVT::f16 || StoreVT == MVT::v2f16 || StoreVT == MVT::v4f16) {
+        if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS ||
+            !BaseOpcode->HasD16)
----------------
I think we already have a hasD16 feature?


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:4527
+        if (LoadVT.isVector() && (Unpacked || !isTypeLegal(LoadVT))) {
+          // TODO simplify this for the packed case once v4f16 is legal
+          if (LoadVT == MVT::v2f16) {
----------------
I'm going to be committing that patch soon so might as well just wait for that


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:4550
+      SDValue Undef = DAG.getUNDEF(Op.getValueType());
+      if (isa<MemSDNode>(Op))
+        return DAG.getMergeValues({ Undef, Op.getOperand(0) }, DL);
----------------
Isn't this always the case?


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:4565-4566
+
+  SDValue True = DAG.getTargetConstant(1, DL, MVT::i32);
+  SDValue False = DAG.getTargetConstant(0, DL, MVT::i32);
+  unsigned CtrlIdx; // Index of texfailctrl argument
----------------
i1?


Repository:
  rL LLVM

https://reviews.llvm.org/D48017