[PATCH] D47721: [X86] Fix skylake server scheduling info.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM with a few final minor corrections.



================
Comment at: lib/Target/X86/X86SchedSkylakeServer.td:978
+def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
+                                          VCVTPD2QQZrr,
+                                          VCVTPD2UQQZrr,
----------------
Keep these aligned


================
Comment at: lib/Target/X86/X86SchedSkylakeServer.td:1091
                                              "(V?)CVTSD2SSrr",
+                                             "VCVTSD2SSZrr",
                                              "(V?)CVTSI(64)?2SDrr",
----------------
Merge this into "(V?)CVTSD2SS(Z?)rr" ?


================
Comment at: lib/Target/X86/X86SchedSkylakeServer.td:1394
+}
+def: InstRW<[SKXWriteResGroup93z], (instregex "VCVTDQ2PDZrr",
+                                              "VCVTPD2DQZrr",
----------------
Don't use instregex unless you really need to - it take a lot longer than a basic instrs match. All of these look like they will have a single match?


Repository:
  rL LLVM

https://reviews.llvm.org/D47721