[PATCH] D31287: [mips] Fix atomic compare and swap at O0, v3

[Simon Dardis via Phabricator via llvm-commits]

sdardis added inline comments.


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Comment at: lib/Target/Mips/MipsISelLowering.cpp:1700-1704
+                           RegState::Dead | RegState::Implicit)
+      .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
+                            RegState::Dead | RegState::Implicit)
+      .addReg(Scratch3, RegState::EarlyClobber | RegState::Define |
+                            RegState::Dead | RegState::Implicit);
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smaksimovic wrote:
> Indentation
This is weird, but it is the output of clang-format.


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Comment at: lib/Target/Mips/MipsISelLowering.cpp:1768
+      .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
+                           RegState::Dead | RegState::Implicit);
 
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smaksimovic wrote:
> Indentation
This is clang-formatted.


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Comment at: lib/Target/Mips/MipsTargetMachine.cpp:288-290
+void MipsPassConfig::addPreSched2() {
+  addPass(createMipsExpandPseudoPass());
+}
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asb wrote:
> Would it be more robust to have this pass under addPreEmit2? This guarantees it runs after potentially troublesome passes such as the machineoutliner (obviously not yet enabled for Mips anyway), and you'd no longer need to worry about machine block placement.
I hadn't considered that yet. Most of my concerns were about making sure the register allocator didn't break the scratch registers by making them non-unique with the address or data registers for the pseudo instruction.


Repository:
  rL LLVM

https://reviews.llvm.org/D31287