[PATCH] D48000: [InstSimplify]update simplifyUnsignedRangeCheck function's test case.

[Li Jia He via Phabricator via llvm-commits]

HLJ2009 created this revision.
Herald added a subscriber: llvm-commits.

Repository:
  rL LLVM

https://reviews.llvm.org/D48000

Files:
  test/Transforms/InstSimplify/AndOrXor.ll


Index: test/Transforms/InstSimplify/AndOrXor.ll
===================================================================
--- test/Transforms/InstSimplify/AndOrXor.ll
+++ test/Transforms/InstSimplify/AndOrXor.ll
@@ -374,14 +374,35 @@
 
 define i1 @and_icmp2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @and_icmp2(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %1 = icmp ugt i32 %x, %y
+  %2 = icmp ne i32 %x, 0
+  %3 = and i1 %1, %2
+  ret i1 %3
+}
+
+define i1 @and_icmp3(i32 %x, i32 %y) {
+; CHECK-LABEL: @and_icmp3(
 ; CHECK-NEXT:    ret i1 false
 ;
   %1 = icmp ult i32 %x, %y
   %2 = icmp eq i32 %y, 0
   %3 = and i1 %1, %2
   ret i1 %3
 }
 
+define i1 @and_icmp4(i32 %x, i32 %y) {
+; CHECK-LABEL: @and_icmp4(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = icmp ugt i32 %x, %y
+  %2 = icmp eq i32 %x, 0
+  %3 = and i1 %1, %2
+  ret i1 %3
+}
+
 define i1 @or_icmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
@@ -395,16 +416,37 @@
 
 define i1 @or_icmp2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp2(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %1 = icmp ugt i32 %x, %y
+  %2 = icmp ne i32 %x, 0
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
+define i1 @or_icmp3(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp3(
 ; CHECK-NEXT:    ret i1 true
 ;
   %1 = icmp uge i32 %x, %y
   %2 = icmp ne i32 %y, 0
   %3 = or i1 %1, %2
   ret i1 %3
 }
 
-define i1 @or_icmp3(i32 %x, i32 %y) {
-; CHECK-LABEL: @or_icmp3(
+define i1 @or_icmp4(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp4(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = icmp ule i32 %x, %y
+  %2 = icmp ne i32 %x, 0
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
+define i1 @or_icmp5(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp5(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
@@ -414,6 +456,17 @@
   ret i1 %3
 }
 
+define i1 @or_icmp6(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp6(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %1 = icmp ule i32 %x, %y
+  %2 = icmp eq i32 %x, 0
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
 ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
 
 define i32 @and_of_zexted_icmps(i32 %i) {


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