[llvm] r334345 - [X86] NFC Use member initialization in X86Subtarget
Gabor Buella via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 9 02:19:41 PDT 2018
Author: gbuella
Date: Sat Jun 9 02:19:40 2018
New Revision: 334345
URL: http://llvm.org/viewvc/llvm-project?rev=334345&view=rev
Log:
[X86] NFC Use member initialization in X86Subtarget
The separate initializeEnvironment function was sort of
useless since r217071.
ARM did this move already with r273556.
Modified:
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=334345&r1=334344&r2=334345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sat Jun 9 02:19:40 2018
@@ -263,117 +263,8 @@ void X86Subtarget::initSubtargetFeatures
PreferVectorWidth = 256;
}
-void X86Subtarget::initializeEnvironment() {
- X86SSELevel = NoSSE;
- X863DNowLevel = NoThreeDNow;
- HasX87 = false;
- HasNOPL = false;
- HasCMov = false;
- HasX86_64 = false;
- HasPOPCNT = false;
- HasSSE4A = false;
- HasAES = false;
- HasVAES = false;
- HasFXSR = false;
- HasXSAVE = false;
- HasXSAVEOPT = false;
- HasXSAVEC = false;
- HasXSAVES = false;
- HasPCLMUL = false;
- HasVPCLMULQDQ = false;
- HasGFNI = false;
- HasFMA = false;
- HasFMA4 = false;
- HasXOP = false;
- HasTBM = false;
- HasLWP = false;
- HasMOVBE = false;
- HasRDRAND = false;
- HasF16C = false;
- HasFSGSBase = false;
- HasLZCNT = false;
- HasBMI = false;
- HasBMI2 = false;
- HasVBMI = false;
- HasVBMI2 = false;
- HasIFMA = false;
- HasRTM = false;
- HasERI = false;
- HasCDI = false;
- HasPFI = false;
- HasDQI = false;
- HasVPOPCNTDQ = false;
- HasBWI = false;
- HasVLX = false;
- HasADX = false;
- HasPKU = false;
- HasVNNI = false;
- HasBITALG = false;
- HasSHA = false;
- HasPREFETCHWT1 = false;
- HasPRFCHW = false;
- HasRDSEED = false;
- HasLAHFSAHF = false;
- HasMWAITX = false;
- HasCLZERO = false;
- HasCLDEMOTE = false;
- HasMOVDIRI = false;
- HasMOVDIR64B = false;
- HasPTWRITE = false;
- HasMPX = false;
- HasSHSTK = false;
- HasINVPCID = false;
- HasSGX = false;
- HasPCONFIG = false;
- HasCLFLUSHOPT = false;
- HasCLWB = false;
- HasWBNOINVD = false;
- HasRDPID = false;
- HasWAITPKG = false;
- UseRetpoline = false;
- UseRetpolineExternalThunk = false;
- IsPMULLDSlow = false;
- IsSHLDSlow = false;
- IsUAMem16Slow = false;
- IsUAMem32Slow = false;
- HasSSEUnalignedMem = false;
- HasCmpxchg16b = false;
- UseLeaForSP = false;
- HasPOPCNTFalseDeps = false;
- HasLZCNTFalseDeps = false;
- HasFastVariableShuffle = false;
- HasFastPartialYMMorZMMWrite = false;
- HasFast11ByteNOP = false;
- HasFast15ByteNOP = false;
- HasFastGather = false;
- HasFastScalarFSQRT = false;
- HasFastVectorFSQRT = false;
- HasFastLZCNT = false;
- HasFastSHLDRotate = false;
- HasMacroFusion = false;
- HasERMSB = false;
- HasSlowDivide32 = false;
- HasSlowDivide64 = false;
- PadShortFunctions = false;
- SlowTwoMemOps = false;
- LEAUsesAG = false;
- SlowLEA = false;
- Slow3OpsLEA = false;
- SlowIncDec = false;
- stackAlignment = 4;
- // FIXME: this is a known good value for Yonah. How about others?
- MaxInlineSizeThreshold = 128;
- UseSoftFloat = false;
- X86ProcFamily = Others;
- GatherOverhead = 1024;
- ScatterOverhead = 1024;
- PreferVectorWidth = UINT32_MAX;
- Prefer256Bit = false;
-}
-
X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
- initializeEnvironment();
initSubtargetFeatures(CPU, FS);
return *this;
}
@@ -383,7 +274,7 @@ X86Subtarget::X86Subtarget(const Triple
unsigned StackAlignOverride,
unsigned PreferVectorWidthOverride,
unsigned RequiredVectorWidth)
- : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
+ : X86GenSubtargetInfo(TT, CPU, FS),
PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
StackAlignOverride(StackAlignOverride),
PreferVectorWidthOverride(PreferVectorWidthOverride),
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=334345&r1=334344&r2=334345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Sat Jun 9 02:19:40 2018
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/Target/TargetMachine.h"
+#include <climits>
#include <memory>
#define GET_SUBTARGETINFO_HEADER
@@ -78,7 +79,7 @@ protected:
};
/// X86 processor family: Intel Atom, and others
- X86ProcFamilyEnum X86ProcFamily;
+ X86ProcFamilyEnum X86ProcFamily = Others;
/// Which PIC style to use
PICStyles::Style PICStyle;
@@ -86,325 +87,326 @@ protected:
const TargetMachine &TM;
/// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
- X86SSEEnum X86SSELevel;
+ X86SSEEnum X86SSELevel = NoSSE;
/// MMX, 3DNow, 3DNow Athlon, or none supported.
- X863DNowEnum X863DNowLevel;
+ X863DNowEnum X863DNowLevel = NoThreeDNow;
/// True if the processor supports X87 instructions.
- bool HasX87;
+ bool HasX87 = false;
/// True if this processor has NOPL instruction
/// (generally pentium pro+).
- bool HasNOPL;
+ bool HasNOPL = false;
/// True if this processor has conditional move instructions
/// (generally pentium pro+).
- bool HasCMov;
+ bool HasCMov = false;
/// True if the processor supports X86-64 instructions.
- bool HasX86_64;
+ bool HasX86_64 = false;
/// True if the processor supports POPCNT.
- bool HasPOPCNT;
+ bool HasPOPCNT = false;
/// True if the processor supports SSE4A instructions.
- bool HasSSE4A;
+ bool HasSSE4A = false;
/// Target has AES instructions
- bool HasAES;
- bool HasVAES;
+ bool HasAES = false;
+ bool HasVAES = false;
/// Target has FXSAVE/FXRESTOR instructions
- bool HasFXSR;
+ bool HasFXSR = false;
/// Target has XSAVE instructions
- bool HasXSAVE;
+ bool HasXSAVE = false;
/// Target has XSAVEOPT instructions
- bool HasXSAVEOPT;
+ bool HasXSAVEOPT = false;
/// Target has XSAVEC instructions
- bool HasXSAVEC;
+ bool HasXSAVEC = false;
/// Target has XSAVES instructions
- bool HasXSAVES;
+ bool HasXSAVES = false;
/// Target has carry-less multiplication
- bool HasPCLMUL;
- bool HasVPCLMULQDQ;
+ bool HasPCLMUL = false;
+ bool HasVPCLMULQDQ = false;
/// Target has Galois Field Arithmetic instructions
- bool HasGFNI;
+ bool HasGFNI = false;
/// Target has 3-operand fused multiply-add
- bool HasFMA;
+ bool HasFMA = false;
/// Target has 4-operand fused multiply-add
- bool HasFMA4;
+ bool HasFMA4 = false;
/// Target has XOP instructions
- bool HasXOP;
+ bool HasXOP = false;
/// Target has TBM instructions.
- bool HasTBM;
+ bool HasTBM = false;
/// Target has LWP instructions
- bool HasLWP;
+ bool HasLWP = false;
/// True if the processor has the MOVBE instruction.
- bool HasMOVBE;
+ bool HasMOVBE = false;
/// True if the processor has the RDRAND instruction.
- bool HasRDRAND;
+ bool HasRDRAND = false;
/// Processor has 16-bit floating point conversion instructions.
- bool HasF16C;
+ bool HasF16C = false;
/// Processor has FS/GS base insturctions.
- bool HasFSGSBase;
+ bool HasFSGSBase = false;
/// Processor has LZCNT instruction.
- bool HasLZCNT;
+ bool HasLZCNT = false;
/// Processor has BMI1 instructions.
- bool HasBMI;
+ bool HasBMI = false;
/// Processor has BMI2 instructions.
- bool HasBMI2;
+ bool HasBMI2 = false;
/// Processor has VBMI instructions.
- bool HasVBMI;
+ bool HasVBMI = false;
/// Processor has VBMI2 instructions.
- bool HasVBMI2;
+ bool HasVBMI2 = false;
/// Processor has Integer Fused Multiply Add
- bool HasIFMA;
+ bool HasIFMA = false;
/// Processor has RTM instructions.
- bool HasRTM;
+ bool HasRTM = false;
/// Processor has ADX instructions.
- bool HasADX;
+ bool HasADX = false;
/// Processor has SHA instructions.
- bool HasSHA;
+ bool HasSHA = false;
/// Processor has PRFCHW instructions.
- bool HasPRFCHW;
+ bool HasPRFCHW = false;
/// Processor has RDSEED instructions.
- bool HasRDSEED;
+ bool HasRDSEED = false;
/// Processor has LAHF/SAHF instructions.
- bool HasLAHFSAHF;
+ bool HasLAHFSAHF = false;
/// Processor has MONITORX/MWAITX instructions.
- bool HasMWAITX;
+ bool HasMWAITX = false;
/// Processor has Cache Line Zero instruction
- bool HasCLZERO;
+ bool HasCLZERO = false;
/// Processor has Cache Line Demote instruction
- bool HasCLDEMOTE;
+ bool HasCLDEMOTE = false;
/// Processor has MOVDIRI instruction (direct store integer).
- bool HasMOVDIRI;
+ bool HasMOVDIRI = false;
/// Processor has MOVDIR64B instruction (direct store 64 bytes).
- bool HasMOVDIR64B;
+ bool HasMOVDIR64B = false;
/// Processor has ptwrite instruction.
- bool HasPTWRITE;
+ bool HasPTWRITE = false;
/// Processor has Prefetch with intent to Write instruction
- bool HasPREFETCHWT1;
+ bool HasPREFETCHWT1 = false;
/// True if SHLD instructions are slow.
- bool IsSHLDSlow;
+ bool IsSHLDSlow = false;
/// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
// PMULUDQ.
- bool IsPMULLDSlow;
+ bool IsPMULLDSlow = false;
/// True if unaligned memory accesses of 16-bytes are slow.
- bool IsUAMem16Slow;
+ bool IsUAMem16Slow = false;
/// True if unaligned memory accesses of 32-bytes are slow.
- bool IsUAMem32Slow;
+ bool IsUAMem32Slow = false;
/// True if SSE operations can have unaligned memory operands.
/// This may require setting a configuration bit in the processor.
- bool HasSSEUnalignedMem;
+ bool HasSSEUnalignedMem = false;
/// True if this processor has the CMPXCHG16B instruction;
/// this is true for most x86-64 chips, but not the first AMD chips.
- bool HasCmpxchg16b;
+ bool HasCmpxchg16b = false;
/// True if the LEA instruction should be used for adjusting
/// the stack pointer. This is an optimization for Intel Atom processors.
- bool UseLeaForSP;
+ bool UseLeaForSP = false;
/// True if POPCNT instruction has a false dependency on the destination register.
- bool HasPOPCNTFalseDeps;
+ bool HasPOPCNTFalseDeps = false;
/// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
- bool HasLZCNTFalseDeps;
+ bool HasLZCNTFalseDeps = false;
/// True if its preferable to combine to a single shuffle using a variable
/// mask over multiple fixed shuffles.
- bool HasFastVariableShuffle;
+ bool HasFastVariableShuffle = false;
/// True if there is no performance penalty to writing only the lower parts
/// of a YMM or ZMM register without clearing the upper part.
- bool HasFastPartialYMMorZMMWrite;
+ bool HasFastPartialYMMorZMMWrite = false;
/// True if there is no performance penalty for writing NOPs with up to
/// 11 bytes.
- bool HasFast11ByteNOP;
+ bool HasFast11ByteNOP = false;
/// True if there is no performance penalty for writing NOPs with up to
/// 15 bytes.
- bool HasFast15ByteNOP;
+ bool HasFast15ByteNOP = false;
/// True if gather is reasonably fast. This is true for Skylake client and
/// all AVX-512 CPUs.
- bool HasFastGather;
+ bool HasFastGather = false;
/// True if hardware SQRTSS instruction is at least as fast (latency) as
/// RSQRTSS followed by a Newton-Raphson iteration.
- bool HasFastScalarFSQRT;
+ bool HasFastScalarFSQRT = false;
/// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
/// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
- bool HasFastVectorFSQRT;
+ bool HasFastVectorFSQRT = false;
/// True if 8-bit divisions are significantly faster than
/// 32-bit divisions and should be used when possible.
- bool HasSlowDivide32;
+ bool HasSlowDivide32 = false;
/// True if 32-bit divides are significantly faster than
/// 64-bit divisions and should be used when possible.
- bool HasSlowDivide64;
+ bool HasSlowDivide64 = false;
/// True if LZCNT instruction is fast.
- bool HasFastLZCNT;
+ bool HasFastLZCNT = false;
/// True if SHLD based rotate is fast.
- bool HasFastSHLDRotate;
+ bool HasFastSHLDRotate = false;
/// True if the processor supports macrofusion.
- bool HasMacroFusion;
+ bool HasMacroFusion = false;
/// True if the processor has enhanced REP MOVSB/STOSB.
- bool HasERMSB;
+ bool HasERMSB = false;
/// True if the short functions should be padded to prevent
/// a stall when returning too early.
- bool PadShortFunctions;
+ bool PadShortFunctions = false;
/// True if two memory operand instructions should use a temporary register
/// instead.
- bool SlowTwoMemOps;
+ bool SlowTwoMemOps = false;
/// True if the LEA instruction inputs have to be ready at address generation
/// (AG) time.
- bool LEAUsesAG;
+ bool LEAUsesAG = false;
/// True if the LEA instruction with certain arguments is slow
- bool SlowLEA;
+ bool SlowLEA = false;
/// True if the LEA instruction has all three source operands: base, index,
/// and offset or if the LEA instruction uses base and index registers where
/// the base is EBP, RBP,or R13
- bool Slow3OpsLEA;
+ bool Slow3OpsLEA = false;
/// True if INC and DEC instructions are slow when writing to flags
- bool SlowIncDec;
+ bool SlowIncDec = false;
/// Processor has AVX-512 PreFetch Instructions
- bool HasPFI;
+ bool HasPFI = false;
/// Processor has AVX-512 Exponential and Reciprocal Instructions
- bool HasERI;
+ bool HasERI = false;
/// Processor has AVX-512 Conflict Detection Instructions
- bool HasCDI;
+ bool HasCDI = false;
/// Processor has AVX-512 population count Instructions
- bool HasVPOPCNTDQ;
+ bool HasVPOPCNTDQ = false;
/// Processor has AVX-512 Doubleword and Quadword instructions
- bool HasDQI;
+ bool HasDQI = false;
/// Processor has AVX-512 Byte and Word instructions
- bool HasBWI;
+ bool HasBWI = false;
/// Processor has AVX-512 Vector Length eXtenstions
- bool HasVLX;
+ bool HasVLX = false;
/// Processor has PKU extenstions
- bool HasPKU;
+ bool HasPKU = false;
/// Processor has AVX-512 Vector Neural Network Instructions
- bool HasVNNI;
+ bool HasVNNI = false;
/// Processor has AVX-512 Bit Algorithms instructions
- bool HasBITALG;
+ bool HasBITALG = false;
/// Processor supports MPX - Memory Protection Extensions
- bool HasMPX;
+ bool HasMPX = false;
/// Processor supports CET SHSTK - Control-Flow Enforcement Technology
/// using Shadow Stack
- bool HasSHSTK;
+ bool HasSHSTK = false;
/// Processor supports Invalidate Process-Context Identifier
- bool HasINVPCID;
+ bool HasINVPCID = false;
/// Processor has Software Guard Extensions
- bool HasSGX;
+ bool HasSGX = false;
/// Processor supports Flush Cache Line instruction
- bool HasCLFLUSHOPT;
+ bool HasCLFLUSHOPT = false;
/// Processor supports Cache Line Write Back instruction
- bool HasCLWB;
+ bool HasCLWB = false;
/// Processor supports Write Back No Invalidate instruction
- bool HasWBNOINVD;
+ bool HasWBNOINVD = false;
/// Processor support RDPID instruction
- bool HasRDPID;
+ bool HasRDPID = false;
/// Processor supports WaitPKG instructions
- bool HasWAITPKG;
+ bool HasWAITPKG = false;
/// Processor supports PCONFIG instruction
- bool HasPCONFIG;
+ bool HasPCONFIG = false;
/// Use a retpoline thunk rather than indirect calls to block speculative
/// execution.
- bool UseRetpoline;
+ bool UseRetpoline = false;
/// When using a retpoline thunk, call an externally provided thunk rather
/// than emitting one inside the compiler.
- bool UseRetpolineExternalThunk;
+ bool UseRetpolineExternalThunk = false;
/// Use software floating point for code generation.
- bool UseSoftFloat;
+ bool UseSoftFloat = false;
/// The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
- unsigned stackAlignment;
+ unsigned stackAlignment = 4;
/// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
///
- unsigned MaxInlineSizeThreshold;
+ // FIXME: this is a known good value for Yonah. How about others?
+ unsigned MaxInlineSizeThreshold = 128;
/// Indicates target prefers 256 bit instructions.
- bool Prefer256Bit;
+ bool Prefer256Bit = false;
/// What processor and OS we're targeting.
Triple TargetTriple;
@@ -424,7 +426,7 @@ private:
/// Resolved preferred vector width from function attribute and subtarget
/// features.
- unsigned PreferVectorWidth;
+ unsigned PreferVectorWidth = UINT32_MAX;
/// Required vector width from function attribute.
unsigned RequiredVectorWidth;
@@ -439,8 +441,8 @@ private:
bool In16BitMode;
/// Contains the Overhead of gather\scatter instructions
- int GatherOverhead;
- int ScatterOverhead;
+ int GatherOverhead = 1024;
+ int ScatterOverhead = 1024;
X86SelectionDAGInfo TSInfo;
// Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
@@ -499,7 +501,6 @@ private:
/// Initialize the full set of dependencies so we can use an initializer
/// list for X86Subtarget.
X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
- void initializeEnvironment();
void initSubtargetFeatures(StringRef CPU, StringRef FS);
public:
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