[PATCH] D47907: [tablegen] Improve performance on *GenRegisterInfo.inc by replacing SparseVector with BitVector. NFC
Daniel Sanders via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 8 16:16:46 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL334337: [tablegen] Improve performance on *GenRegisterInfo.inc by replacing… (authored by dsanders, committed by ).
Repository:
rL LLVM
https://reviews.llvm.org/D47907
Files:
llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
Index: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
@@ -21,7 +21,6 @@
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/SparseBitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
@@ -1635,9 +1634,10 @@
static bool normalizeWeight(CodeGenRegister *Reg,
std::vector<UberRegSet> &UberSets,
std::vector<UberRegSet*> &RegSets,
- SparseBitVector<> &NormalRegs,
+ BitVector &NormalRegs,
CodeGenRegister::RegUnitList &NormalUnits,
CodeGenRegBank &RegBank) {
+ NormalRegs.resize(std::max(Reg->EnumValue + 1, NormalRegs.size()));
if (NormalRegs.test(Reg->EnumValue))
return false;
NormalRegs.set(Reg->EnumValue);
@@ -1711,7 +1711,7 @@
Changed = false;
for (auto &Reg : Registers) {
CodeGenRegister::RegUnitList NormalUnits;
- SparseBitVector<> NormalRegs;
+ BitVector NormalRegs;
Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
NormalUnits, *this);
}
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