[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

In https://reviews.llvm.org/D46356#1126217, @RKSimon wrote:

> @evandro Does AArch64SchedExynosM1.td and AArch64SchedThunderX2T99.td look correct now please?


Except for my remark above on https://reviews.llvm.org/M1, the changes to X2T99 seem reasonable to me.  But I am not familiar with this Cavium processor.  It'd be better if someone from Cavium would chime in, but their silence, after so long, might be taken as consent.


Repository:
  rL LLVM

https://reviews.llvm.org/D46356