[llvm] r334268 - [DAGCombine] Fix for PR37667
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 8 00:49:04 PDT 2018
Author: sam_parker
Date: Fri Jun 8 00:49:04 2018
New Revision: 334268
URL: http://llvm.org/viewvc/llvm-project?rev=334268&view=rev
Log:
[DAGCombine] Fix for PR37667
While trying to propagate AND masks back to loads, we currently allow
one non-load node to be included as a leaf in chain. This fix now
limits that node to produce only a single data value.
Differential Revision: https://reviews.llvm.org/D47878
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/backpropmask.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=334268&r1=334267&r2=334268&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun 8 00:49:04 2018
@@ -3997,7 +3997,23 @@ bool DAGCombiner::SearchForAndLoads(SDNo
// Allow one node which will masked along with any loads found.
if (NodeToMask)
return false;
+
+ // Also ensure that the node to be masked only produces one data result.
NodeToMask = Op.getNode();
+ if (NodeToMask->getNumValues() > 1) {
+ bool HasValue = false;
+ for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
+ MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
+ if (VT != MVT::Glue && VT != MVT::Other) {
+ if (HasValue) {
+ NodeToMask = nullptr;
+ return false;
+ }
+ HasValue = true;
+ }
+ }
+ assert(HasValue && "Node to be masked has no data result?");
+ }
}
return true;
}
Modified: llvm/trunk/test/CodeGen/X86/backpropmask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/backpropmask.ll?rev=334268&r1=334267&r2=334268&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/backpropmask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/backpropmask.ll Fri Jun 8 00:49:04 2018
@@ -1,11 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
-; FIXME:
-; Verify that backwards propagation of a mask does not affect
-; nodes with multiple result values. In both tests, the stored
-; 32-bit value should be masked to an 8-bit number (and 255).
-
@b = local_unnamed_addr global i32 918, align 4
@d = local_unnamed_addr global i32 8089, align 4
@c = common local_unnamed_addr global i32 0, align 4
@@ -14,12 +9,12 @@
define void @PR37667() {
; CHECK-LABEL: PR37667:
; CHECK: # %bb.0:
-; CHECK-NEXT: movzbl {{.*}}(%rip), %ecx
; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl {{.*}}(%rip)
-; CHECK-NEXT: orl %ecx, %edx
-; CHECK-NEXT: movl %edx, {{.*}}(%rip)
+; CHECK-NEXT: orl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzbl %dl, %eax
+; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: retq
%t0 = load i32, i32* @c, align 4
%t1 = load i32, i32* @b, align 4
@@ -37,8 +32,8 @@ define void @PR37060() {
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl {{.*}}(%rip)
-; CHECK-NEXT: movzbl {{.*}}(%rip), %eax
-; CHECK-NEXT: xorl %edx, %eax
+; CHECK-NEXT: xorl {{.*}}(%rip), %edx
+; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: retq
%t0 = load i32, i32* @c, align 4
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