[PATCH] D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: jyknight, theraven, eli.friedman, jfb.
Herald added subscribers: atanasyan, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, kristof.beyls, arichardson, mgorny, sdardis.
Herald added a reviewer: javed.absar.

Introduce a new RISCVExpandPseudoInsts pass to expand atomic pseudo-instructions after register allocation. This is necessary in order to ensure that register spills aren't introduced between LL and SC, thus breaking the forward progress guarantee for the operation. AArch64 does something similar for CmpXchg (though only at O0), and Mips is moving towards this approach (see https://reviews.llvm.org/D31287). See also [this mailing list post]http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html) from James Knight, which summarises the issues with lowering to ll/sc in IR or pre-RA. I have some further thoughts on how to improve the handling of this, which I'll follow-up with on llvm-dev.

More efficient mappings are possible for some of the partword AMOs, e.g.
8/16-bit bitwise AMO can use the native word-wize operations when appropriate
masking is used.


https://reviews.llvm.org/D47882

Files:
  lib/Target/RISCV/CMakeLists.txt
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoA.td
  lib/Target/RISCV/RISCVTargetMachine.cpp
  test/CodeGen/RISCV/atomic-rmw.ll

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