[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 150324.
asb marked 2 inline comments as done.
asb added a comment.

Update to address all outstanding review comments.

I've also removed part-world (i8/i16) atomicrmw min/max/umin/umax from atomic-rmw.ll, as they will not be supported in the first round of RV32A patches and are non-standard (Clang will refuse to generate them, and they're unsupported on other archs like Mips).


https://reviews.llvm.org/D47587

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVTargetMachine.cpp
  test/CodeGen/RISCV/atomic-cmpxchg.ll
  test/CodeGen/RISCV/atomic-fence.ll
  test/CodeGen/RISCV/atomic-load-store.ll
  test/CodeGen/RISCV/atomic-rmw.ll

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