[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

In https://reviews.llvm.org/D46356#1120407, @courbet wrote:

> A review of ExynosM1 /ThunderX2, as I'm not familiar with these CPUs.


I'm sorry, I completely forgot about https://reviews.llvm.org/M1.



================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:329
                                                      let NumMicroOps = 2;
-                                                     let ResourceCycles = [5]; }
+                                                     let ResourceCycles = [5, 1]; }
 def M1WriteVLDG    : SchedWriteRes<[M1UnitL,
----------------
[1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:343
                                                      let NumMicroOps = 3;
-                                                     let ResourceCycles = [6]; }
+                                                     let ResourceCycles = [6, 1, 1]; }
 def M1WriteVLDJ    : SchedWriteRes<[M1UnitL,
----------------
[2, 2, 2]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:349
                                                      let NumMicroOps = 4;
-                                                     let ResourceCycles = [4]; }
+                                                     let ResourceCycles = [4, 1, 1, 1]; }
 def M1WriteVLDK    : SchedWriteRes<[M1UnitL,
----------------
[2, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:356
                                                      let NumMicroOps = 5;
-                                                     let ResourceCycles = [4]; }
+                                                     let ResourceCycles = [4, 1, 1, 1, 1]; }
 def M1WriteVLDL    : SchedWriteRes<[M1UnitL,
----------------
[2, 1, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:363
                                                      let NumMicroOps = 5;
-                                                     let ResourceCycles = [2]; }
+                                                     let ResourceCycles = [2, 1, 1, 1, 1]; }
 def M1WriteVLDM    : SchedWriteRes<[M1UnitL,
----------------
[1, 1, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:371
                                                      let NumMicroOps = 6;
-                                                     let ResourceCycles = [2]; }
+                                                     let ResourceCycles = [2, 1, 1, 1, 1, 1]; }
 def M1WriteVLDN    : SchedWriteRes<[M1UnitL,
----------------
[1, 1, 1, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:377
                                                      let NumMicroOps = 4;
-                                                     let ResourceCycles = [7]; }
+                                                     let ResourceCycles = [7, 1, 1, 1]; }
 def M1WriteVSTA    : WriteSequence<[WriteVST], 2>;
----------------
[2, 1, 2, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:392
                                                      let NumMicroOps = 3;
-                                                     let ResourceCycles = [8]; }
+                                                     let ResourceCycles = [8, 1, 1, 1, 1]; }
 def M1WriteVSTF    : SchedWriteRes<[M1UnitNALU,
----------------
[7, 1, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:401
                                                       let NumMicroOps = 5;
-                                                      let ResourceCycles = [15]; }
+                                                      let ResourceCycles = [15, 1, 1, 1, 1, 1, 1]; }
 def M1WriteVSTG    : SchedWriteRes<[M1UnitNALU,
----------------
[1, 7, 1, 7, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:412
                                                       let NumMicroOps = 6;
-                                                      let ResourceCycles = [16]; }
+                                                      let ResourceCycles = [16, 1, 1, 1, 1, 1, 1, 1, 1]; }
 def M1WriteVSTH    : SchedWriteRes<[M1UnitNALU,
----------------
[1, 7, 1, 7, 1, 1, 1, 1, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:419
                                                        let NumMicroOps = 4;
-                                                       let ResourceCycles = [14]; }
+                                                       let ResourceCycles = [14, 1, 1, 1, 1]; }
 def M1WriteVSTI    : SchedWriteRes<[M1UnitNALU,
----------------
[1, 7, 1, 7, 1]


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:432
                                                        let NumMicroOps = 7;
-                                                       let ResourceCycles = [17]; }
+                                                       let ResourceCycles = [17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]; }
 
----------------
[1, 7, 1, 7, 1, 1, 1, 1, 1, 1, 1]


Repository:
  rL LLVM

https://reviews.llvm.org/D46356