[llvm] r334038 - [Hexagon] Add more patterns for generating abs/absp instructions

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Jun  5 12:00:50 2018
New Revision: 334038

URL: http://llvm.org/viewvc/llvm-project?rev=334038&view=rev
Log:
[Hexagon] Add more patterns for generating abs/absp instructions

Added:
    llvm/trunk/test/CodeGen/Hexagon/abs.ll
Removed:
    llvm/trunk/test/CodeGen/Hexagon/integer_abs.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=334038&r1=334037&r2=334038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Tue Jun  5 12:00:50 2018
@@ -1158,6 +1158,7 @@ def: Pat<(shl V4I16:$b, (v4i16 (HexagonV
 //
 
 def: Pat<(abs I32:$Rs), (A2_abs   I32:$Rs)>;
+def: Pat<(abs I64:$Rs), (A2_absp  I64:$Rs)>;
 def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
 def: Pat<(not I64:$Rs), (A2_notp  I64:$Rs)>;
 
@@ -1174,11 +1175,20 @@ let Predicates = [HasV5T] in {
 }
 
 let AddedComplexity = 50 in
-def: Pat<(xor (add (sra I32:$Rs, (i32 31)),
-                   I32:$Rs),
-              (sra I32:$Rs, (i32 31))),
-         (A2_abs I32:$Rs)>;
+multiclass Abs_pat<InstHexagon MI, PatFrag RsPred, int Sh> {
+  // Let y = x >> 31 (for 32-bit), i.e. the sign bit repeated.
+  // abs(x) = (x + y) ^ y
+  def: Pat<(xor (add (sra RsPred:$Rs, (i32 Sh)), RsPred:$Rs),
+                (sra RsPred:$Rs, (i32 Sh))),
+           (MI RsPred:$Rs)>;
+  // abs(x) = (x ^ y) - y
+  def: Pat<(sub (xor RsPred:$Rs, (sra RsPred:$Rs, (i32 Sh))),
+                (sra RsPred:$Rs, (i32 Sh))),
+           (MI RsPred:$Rs)>;
+}
 
+defm: Abs_pat<A2_abs,  I32, 31>;
+defm: Abs_pat<A2_absp, I64, 63>;
 
 def: Pat<(add I32:$Rs, anyimm:$s16),   (A2_addi   I32:$Rs,  imm:$s16)>;
 def: Pat<(or  I32:$Rs, anyimm:$s10),   (A2_orir   I32:$Rs,  imm:$s10)>;

Added: llvm/trunk/test/CodeGen/Hexagon/abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/abs.ll?rev=334038&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/abs.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/abs.ll Tue Jun  5 12:00:50 2018
@@ -0,0 +1,57 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: f0:
+; CHECK: r0 = abs(r0)
+define i32 @f0(i32 %a0) #0 {
+  %v0 = ashr i32 %a0, 31
+  %v1 = xor i32 %a0, %v0
+  %v2 = sub i32 %v1, %v0
+  ret i32 %v2
+}
+
+; CHECK-LABEL: f1:
+; CHECK: r0 = abs(r0)
+define i32 @f1(i32 %a0) #0 {
+  %v0 = ashr i32 %a0, 31
+  %v1 = add i32 %a0, %v0
+  %v2 = xor i32 %v0, %v1
+  ret i32 %v2
+}
+
+; CHECK-LABEL: f2:
+; CHECK: r0 = abs(r0)
+define i32 @f2(i32 %a0) #0 {
+  %v0 = icmp slt i32 %a0, 0
+  %v1 = sub nsw i32 0, %a0
+  %v2 = select i1 %v0, i32 %v1, i32 %a0
+  ret i32 %v2
+}
+
+; CHECK-LABEL: f3:
+; CHECK: r1:0 = abs(r1:0)
+define i64 @f3(i64 %a0) #0 {
+  %v0 = ashr i64 %a0, 63
+  %v1 = xor i64 %a0, %v0
+  %v2 = sub i64 %v1, %v0
+  ret i64 %v2
+}
+
+; CHECK-LABEL: f4:
+; CHECK: r1:0 = abs(r1:0)
+define i64 @f4(i64 %a0) #0 {
+  %v0 = ashr i64 %a0, 63
+  %v1 = add i64 %a0, %v0
+  %v2 = xor i64 %v0, %v1
+  ret i64 %v2
+}
+
+; CHECK-LABEL: f5:
+; CHECK: r1:0 = abs(r1:0)
+define i64 @f5(i64 %a0) #0 {
+  %v0 = icmp slt i64 %a0, 0
+  %v1 = sub nsw i64 0, %a0
+  %v2 = select i1 %v0, i64 %v1, i64 %a0
+  ret i64 %v2
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }

Removed: llvm/trunk/test/CodeGen/Hexagon/integer_abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/integer_abs.ll?rev=334037&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/integer_abs.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/integer_abs.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
-; Check for integer abs instruction.
-; CHECK: r{{[0-9]+}} = abs
-
-; Function Attrs: nounwind readnone
-define i32 @f0(i32 %a0) #0 {
-b0:
-  %v0 = icmp slt i32 %a0, 0
-  %v1 = sub nsw i32 0, %a0
-  %v2 = select i1 %v0, i32 %v1, i32 %a0
-  ret i32 %v2
-}
-
-attributes #0 = { nounwind readnone }