[llvm] r334011 - [PowerPC] reduce rotate in BitPermutationSelector

[Hiroshi Inoue via llvm-commits]

Author: inouehrs
Date: Tue Jun  5 04:58:01 2018
New Revision: 334011

URL: http://llvm.org/viewvc/llvm-project?rev=334011&view=rev
Log:
[PowerPC] reduce rotate in BitPermutationSelector

BitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers.
Here, we may avoid one rotate instruction if we start building from an input register that does not require rotation.

For example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation.
This can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5.

This patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first.

Differential Revision: https://reviews.llvm.org/D47765


Added:
    llvm/trunk/test/CodeGen/PowerPC/bitfieldinsert.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=334011&r1=334010&r2=334011&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Jun  5 04:58:01 2018
@@ -1161,6 +1161,10 @@ class BitPermutationSelector {
         return true;
       else if (NumGroups < Other.NumGroups)
         return false;
+      else if (RLAmt == 0 && Other.RLAmt != 0)
+        return true;
+      else if (RLAmt != 0 && Other.RLAmt == 0)
+        return false;
       else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
         return true;
       return false;
@@ -1374,7 +1378,9 @@ class BitPermutationSelector {
   }
 
   // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
-  // associated with each. If there is a degeneracy, pick the one that occurs
+  // associated with each. If the number of groups are same, we prefer a group
+  // which does not require rotate, i.e. RLAmt is 0, to avoid the first rotate
+  // instruction. If there is a degeneracy, pick the one that occurs
   // first (in the final value).
   void collectValueRotInfo() {
     ValueRots.clear();

Added: llvm/trunk/test/CodeGen/PowerPC/bitfieldinsert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bitfieldinsert.ll?rev=334011&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/bitfieldinsert.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/bitfieldinsert.ll Tue Jun  5 04:58:01 2018
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; bitfieldinsert32: Test for rlwimi
+; equivalent C code
+;   struct s32 {
+;   	int a:8;
+;   	int b:16;
+;   	int c:8;
+;   };
+;   void bitfieldinsert32(struct s32 *p, unsigned int v) {
+;   	p->b = v;
+;   }
+
+%struct.s32 = type { i32 }
+
+define void @bitfieldinsert32(%struct.s32* nocapture %p, i32 zeroext %v) {
+; CHECK-LABEL: @bitfieldinsert32
+; CHECK: lwz [[REG1:[0-9]+]], 0(3)
+; CHECK: rlwimi [[REG1]], 4, 8, 8, 23
+; CHECK: stw [[REG1]], 0(3)
+; CHECK: blr
+entry:
+  %0 = getelementptr inbounds %struct.s32, %struct.s32* %p, i64 0, i32 0
+  %bf.load = load i32, i32* %0, align 4
+  %bf.value = shl i32 %v, 8
+  %bf.shl = and i32 %bf.value, 16776960
+  %bf.clear = and i32 %bf.load, -16776961
+  %bf.set = or i32 %bf.clear, %bf.shl
+  store i32 %bf.set, i32* %0, align 4
+  ret void
+}
+