[PATCH] D45203: [X86] VRNDSCALE* folding from masked and single-value ffloor and fceil patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:8605
+                                v4f32x_info, fp32imm0, 0x01,
+                                (COPY_TO_REGCLASS $mask, VK1WM), HasVLX>;
+defm : avx512_masked_scalar_imm<ffloor, "RNDSCALESS", X86Movss,
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Why HasVLX? Shouldn't scalar instructions be valid under HasAVX512?


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Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:9777
+def : Pat<(v16f32 (vselect VK16WM:$mask, (ffloor VR512:$src), VR512:$dst)),
+          (VRNDSCALEPSZrrik VR512:$dst, VK16WM:$mask, VR512:$src, (i32 0x9))>;
 def : Pat<(v16f32 (fnearbyint VR512:$src)),
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What about zero masking?


https://reviews.llvm.org/D45203